公开(公告)号：US20240021261A1

公开(公告)日：2024-01-18

申请号：US18475968

申请日：2023-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunhye Oh ,  Jaehyeok Kim ,  Yong Ki Lee ,  Gapkyoung Kim ,  Taewook Park

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/10 ,  G11C29/36

CPC classification number: G11C29/42 ,  G11C29/4401 ,  G11C29/10 ,  G11C29/36

Abstract: A memory device includes a memory module and a BIST logic circuit. The BIST logic circuit includes; a pattern generator configured to generate first main data including a first portion, an error correction code (ECC) encoder configured to generate first parity data based on the first main data, and a parity control circuit configured to generate mask data based on the first parity data and the first main data, and generate first substituted parity data based on the mask data and the first parity data, wherein a pattern of the first substituted parity data is the same as a pattern of the first portion of the first main data.

公开(公告)号：US20240006008A1

公开(公告)日：2024-01-04

申请号：US18314508

申请日：2023-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taewook Park ,  Eunhye Oh ,  Jisu Kang ,  Yongki Lee

IPC: G11C29/36

CPC classification number: G11C29/36 ,  G11C2029/1204

Abstract: An operation method of a memory device includes programming a test pattern in a normal area, obtaining locations of error bits with respect to the test pattern and an error count for each error bit location, and repairing faulty cells included in the normal area with redundancy cells in a redundancy area based on the locations of the error bits and the error counts.

公开(公告)号：US20220404859A1

公开(公告)日：2022-12-22

申请号：US17841078

申请日：2022-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunil Kim ,  Jisu Kang ,  Taewook Park ,  Hongmook Choi

IPC: G06F1/10 ,  G06F1/12

Abstract: A clock generating circuit includes an oscillator, a clock counter, a finite state machine, and a non-volatile memory. The oscillator outputs an oscillator clock signal having a period based on a trim value. The clock counter counts the oscillator clock signal for a reference time. The finite state machine obtains the count value of the counted oscillator clock signal from the clock counter, and in a test mode, compares the count value with a target count value and changes the trim value based on the comparison result and determines a final trim value based on the changed trim value. The non-volatile memory stores the final trim value that is determined.

公开(公告)号：US12169419B2

公开(公告)日：2024-12-17

申请号：US17841078

申请日：2022-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunil Kim ,  Jisu Kang ,  Taewook Park ,  Hongmook Choi

IPC: G06F1/10 ,  G06F1/08 ,  G06F1/12 ,  G11C29/02 ,  G11C29/56 ,  H03K21/38

Abstract: A clock generating circuit includes an oscillator, a clock counter, a finite state machine, and a non-volatile memory. The oscillator outputs an oscillator clock signal having a period based on a trim value. The clock counter counts the oscillator clock signal for a reference time. The finite state machine obtains the count value of the counted oscillator clock signal from the clock counter, and in a test mode, compares the count value with a target count value and changes the trim value based on the comparison result and determines a final trim value based on the changed trim value. The non-volatile memory stores the final trim value that is determined.

公开(公告)号：US12164376B2

公开(公告)日：2024-12-10

申请号：US18148061

申请日：2022-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunhye Oh ,  Taewook Park ,  Jisu Kang ,  Yongki Lee

IPC: G06F11/10 ,  G06F11/07

Abstract: Provided is a storage device including a memory device configured to store original data; and a controller configured to control the memory device, the controller including a first error correction circuit configured to correct an error of the original data, and a second error correction circuit configured to correct an error of the original data, a maximum number of correctable error bits of the second error correction circuit being greater than a maximum number of correctable error bits of the first error correction circuit, a mapping memory configured to store at least some of parity bits generated by the second error correction circuit and store an address of the memory device at which the original data is stored; and a control block configured to control the first error correction circuit, the second error correction circuit, and the mapping memory.

公开(公告)号：US11804276B2

公开(公告)日：2023-10-31

申请号：US17467861

申请日：2021-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunhye Oh ,  Jaehyeok Kim ,  Yong Ki Lee ,  Gapkyoung Kim ,  Taewook Park

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/10 ,  G11C29/36

CPC classification number: G11C29/42 ,  G11C29/10 ,  G11C29/36 ,  G11C29/4401

Abstract: A memory device includes a memory module and a BIST logic circuit. The BIST logic circuit includes; a pattern generator configured to generate first main data including a first portion, an error correction code (ECC) encoder configured to generate first parity data based on the first main data, and a parity control circuit configured to generate mask data based on the first parity data and the first main data, and generate first substituted parity data based on the mask data and the first parity data, wherein a pattern of the first substituted parity data is the same as a pattern of the first portion of the first main data.