公开(公告)号：US10062427B2

公开(公告)日：2018-08-28

申请号：US14722634

申请日：2015-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Whi-Young Bae ,  Young-Sik Kim ,  Young-Yong Byun

IPC: G06F11/10 ,  G11C11/406 ,  G11C11/408 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24

CPC classification number: G11C11/406 ,  G06F11/1048 ,  G11C11/40611 ,  G11C11/408 ,  G11C29/24 ,  G11C29/70 ,  G11C29/74 ,  G11C29/783 ,  G11C29/816 ,  G11C2029/0411 ,  G11C2211/4061

Abstract: Provided is a semiconductor memory device for controlling a refresh operation of redundancy memory cells. The semiconductor memory device may include normal memory cells and redundancy memory cells that are used to repair normal memory cell(s) to which a defective cell is connected, and an error-correction code (ECC) memory cell row that stores parity bits for controlling the defective cell. Memory cells on the normal memory cell rows are refreshed during a first refresh cycle. Other memory cells on, such as redundancy memory cell rows, an edge memory cell row that is adjacent to the redundancy memory cell row(s) from among the normal memory cell rows, and/or the ECC memory cell row may be refreshed during a second refresh cycle that is different from the first refresh cycle.

公开(公告)号：US09601179B2

公开(公告)日：2017-03-21

申请号：US14723261

申请日：2015-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Yong Byun ,  Whi-Young Bae

IPC: G11C7/00 ,  G11C11/406 ,  G11C8/10 ,  G11C11/408 ,  G11C8/04

CPC classification number: G11C11/40618 ,  G11C8/04 ,  G11C8/10 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/408

Abstract: A semiconductor memory device may include a memory cell array, a first decoder and a second decoder. The memory cell array includes a plurality of memory cell rows. The first decoder is configured to select a first number of memory cell rows of the plurality of memory cell rows based on a selected refresh row address of a set of row addresses. The second decoder is configured to select a second number of memory cell rows of the plurality of memory cell rows based on the selected refresh row address. A total number of the first number and the second number is varied in response to the selected refresh row address.