公开(公告)号：US10297451B2

公开(公告)日：2019-05-21

申请号：US15644931

申请日：2017-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Seok Jung ,  Joon Hee Lee ,  Keon Soo Kim ,  Sun Yeong Lee

IPC: H01L27/1157 ,  H01L21/28 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/78

Abstract: A method of manufacturing a memory device includes: providing a substrate; forming in a cell region a channel extending in a direction perpendicular to an upper surface of the substrate and a plurality of gate electrode layers and a plurality of insulating layers stacked alternatingly on the substrate to be adjacent to the channel; forming a plurality of circuit elements on the substrate at a peripheral circuit region disposed at a periphery of the cell region; and forming an interlayer insulating layer on the substrate in the cell region and the peripheral circuit region, the interlayer insulating layer including a first, bottom interlayer insulating layer covering the plurality of circuit elements and at least a portion of the plurality of gate electrode layers, and a second, top interlayer insulating layer disposed on the first interlayer insulating layer.

公开(公告)号：US09735014B2

公开(公告)日：2017-08-15

申请号：US14642668

申请日：2015-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Seok Jung ,  Joon Hee Lee ,  Keon Soo Kim ,  Sun Yeong Lee

IPC: H01L21/336 ,  H01L21/28 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/28008 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method of manufacturing a memory device includes: providing a substrate; forming in a cell region a channel extending in a direction perpendicular to an upper surface of the substrate and a plurality of gate electrode layers and a plurality of insulating layers stacked alternatingly on the substrate to be adjacent to the channel; forming a plurality of circuit elements on the substrate at a peripheral circuit region disposed at a periphery of the cell region; and forming an interlayer insulating layer on the substrate in the cell region and the peripheral circuit region, the interlayer insulating layer including a first, bottom interlayer insulating layer covering the plurality of circuit elements and at least a portion of the plurality of gate electrode layers, and a second, top interlayer insulating layer disposed on the first interlayer insulating layer.