公开(公告)号：US11942956B2

公开(公告)日：2024-03-26

申请号：US17885844

申请日：2022-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Seob Lee ,  Shin Woong Kim ,  Joon Hee Lee ,  Sang Wook Han

IPC: H03L7/099 ,  H03L7/093 ,  H03M1/10

CPC classification number: H03L7/0992 ,  H03L7/093 ,  H03L7/0995 ,  H03M1/1014

Abstract: Provided is a time-to-digital converter, comprising a phase frequency detector configured to receive a phase-locked loop input clock and a feedback clock, a ring oscillator configured to perform oscillation with multi-phase clocks of a first period, a counter array configured to count the number of oscillations in which the ring oscillator oscillates in a first period by the number of positive integers during the first pulse width, a multiplexer configured to divide the first period into a plurality of zones using edge information of the multi-phase clocks of the ring oscillator, and selects and outputs voltage information of a plurality of neighboring phase clocks included in a first zone from the plurality of zones, an analog-to-digital converter, a calibrator, and a first adder, wherein the calibrator comprises, an offset lookup table generation circuit, a gain-corrected analog-to-digital conversion output generator, and a second adder.

公开(公告)号：US10297451B2

公开(公告)日：2019-05-21

申请号：US15644931

申请日：2017-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Seok Jung ,  Joon Hee Lee ,  Keon Soo Kim ,  Sun Yeong Lee

IPC: H01L27/1157 ,  H01L21/28 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/78

Abstract: A method of manufacturing a memory device includes: providing a substrate; forming in a cell region a channel extending in a direction perpendicular to an upper surface of the substrate and a plurality of gate electrode layers and a plurality of insulating layers stacked alternatingly on the substrate to be adjacent to the channel; forming a plurality of circuit elements on the substrate at a peripheral circuit region disposed at a periphery of the cell region; and forming an interlayer insulating layer on the substrate in the cell region and the peripheral circuit region, the interlayer insulating layer including a first, bottom interlayer insulating layer covering the plurality of circuit elements and at least a portion of the plurality of gate electrode layers, and a second, top interlayer insulating layer disposed on the first interlayer insulating layer.

公开(公告)号：US09735014B2

公开(公告)日：2017-08-15

申请号：US14642668

申请日：2015-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Seok Jung ,  Joon Hee Lee ,  Keon Soo Kim ,  Sun Yeong Lee

IPC: H01L21/336 ,  H01L21/28 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/28008 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method of manufacturing a memory device includes: providing a substrate; forming in a cell region a channel extending in a direction perpendicular to an upper surface of the substrate and a plurality of gate electrode layers and a plurality of insulating layers stacked alternatingly on the substrate to be adjacent to the channel; forming a plurality of circuit elements on the substrate at a peripheral circuit region disposed at a periphery of the cell region; and forming an interlayer insulating layer on the substrate in the cell region and the peripheral circuit region, the interlayer insulating layer including a first, bottom interlayer insulating layer covering the plurality of circuit elements and at least a portion of the plurality of gate electrode layers, and a second, top interlayer insulating layer disposed on the first interlayer insulating layer.