公开(公告)号：US20180301456A1

公开(公告)日：2018-10-18

申请号：US15821089

申请日：2017-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Hee Cho ,  Jun Soo Kim ,  Hui Jung Kim ,  Tae Yoon An ,  Satoru Yamada ,  Won Sok Lee ,  Nam Ho Jeon ,  Moon Young Jeong ,  Ki Jae Hur ,  Jae Ho Hong

IPC: H01L27/108 ,  H01L27/12

CPC classification number: H01L27/10802 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10876 ,  H01L27/1207 ,  H01L29/4236

Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.

公开(公告)号：US20230147083A1

公开(公告)日：2023-05-11

申请号：US17846158

申请日：2022-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Hee Cho ,  Dong Il Bae ,  Won Sok Lee ,  Yong Seok Kim

IPC: H01L27/11573 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11526

CPC classification number: H01L27/11573 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11526

Abstract: A semiconductor memory device includes a cell area and a peripheral area, a base insulating layer including opposed first front and rear surfaces in the cell area, a first semiconductor substrate including opposed second front and rear surfaces in the peripheral area, an active pattern on the first front surface, a first conductive line extending in a first direction on a side of the active pattern, a capacitor structure on the active pattern, a first circuit element on the second front surface, and a second conductive line extending in a second direction intersecting the first direction on the first rear surface and the second rear surface. The active pattern extends in a vertical direction intersecting the first direction and the second direction to electrically connect the second conductive line to the capacitor structure.

公开(公告)号：US12080791B2

公开(公告)日：2024-09-03

申请号：US17400218

申请日：2021-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Tae Ryu ,  Sang Hoon Uhm ,  Ki Seok Lee ,  Min Su Lee ,  Won Sok Lee ,  Min Hee Cho

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/24 ,  H10B12/00

CPC classification number: H01L29/7813 ,  H01L27/088 ,  H01L29/24 ,  H10B12/30

Abstract: A semiconductor memory device with improved performance by improving interface characteristics while reducing a leakage current, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line on a substrate, a first interlayer insulating layer exposing the conductive line and defining a channel trench on the substrate, a channel layer extending along a bottom and side surface of the channel trench, a first gate electrode and a second gate electrode spaced apart from each other in the channel trench, a first gate insulating layer between the channel layer and the first gate electrode, and a second gate insulating layer between the channel layer and the second gate electrode. The channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line. The first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.

公开(公告)号：US10770463B2

公开(公告)日：2020-09-08

申请号：US16437784

申请日：2019-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Hee Cho ,  Jun Soo Kim ,  Hui Jung Kim ,  Tae Yoon An ,  Satoru Yamada ,  Won Sok Lee ,  Nam Ho Jeon ,  Moon Young Jeong ,  Ki Jae Hur ,  Jae Ho Hong

IPC: H01L27/108 ,  H01L27/12 ,  H01L21/84 ,  H01L29/423 ,  H01L21/768

Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.

公开(公告)号：US10361205B2

公开(公告)日：2019-07-23

申请号：US15821089

申请日：2017-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Hee Cho ,  Jun Soo Kim ,  Hui Jung Kim ,  Tae Yoon An ,  Satoru Yamada ,  Won Sok Lee ,  Nam Ho Jeon ,  Moon Young Jeong ,  Ki Jae Hur ,  Jae Ho Hong

IPC: H01L27/108 ,  H01L27/12 ,  H01L21/768 ,  H01L29/423

Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.