公开(公告)号：US20220319575A1

公开(公告)日：2022-10-06

申请号：US17705915

申请日：2022-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu Lee ,  Min Tae Ryu ,  Wonsok Lee ,  Min Hee Cho

IPC: G11C11/408

Abstract: Disclosed is a memory device including a row decoder generating word line (WL) control signals based on a row address from an external device, a first sub-array including memory cells connected to word lines, a first sub-word line driver (SWD) providing a selection voltage or a non-selection voltage to odd-numbered word lines of the word lines based on odd-numbered WL control signals corresponding to the odd-numbered word lines, and a second SWD providing the selection voltage or the non-selection voltage to even-numbered word lines of the word lines based on even-numbered WL control signals corresponding to the even-numbered word lines. The first SWD applies the non-selection voltage to non-selection word lines of the even-numbered word lines, in response to the even-numbered WL control signals, and the second SWD applies the non-selection voltage to non-selection word lines of the odd-numbered word lines, in response to the odd-numbered WL control signals.

公开(公告)号：US12075611B2

公开(公告)日：2024-08-27

申请号：US17481583

申请日：2021-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonsok Lee ,  Min Tae Ryu ,  Woo Bin Song ,  Kiseok Lee ,  Minsu Lee ,  Min Hee Cho

IPC: H10B12/00 ,  G11C5/06 ,  H01L29/06

CPC classification number: H10B12/315 ,  G11C5/063 ,  H01L29/0607 ,  H10B12/05 ,  H10B12/50

Abstract: A semiconductor memory includes a bit line extending in a first direction, first and second active patterns, which are alternately disposed in the first direction and on the bit line, and each of which includes a horizontal portion and a vertical portion, first word lines disposed on the horizontal portions of the first active patterns to cross the bit line, second word lines disposed on the horizontal portions of the second active patterns to cross the bit line, and an intermediate structure provided in a first gap region between the first and second word lines or in a second gap region between the vertical portions of the first and second active patterns. The first and second active patterns, which are adjacent to each other, may be disposed to be symmetric with respect to each other.

公开(公告)号：US12080791B2

公开(公告)日：2024-09-03

申请号：US17400218

申请日：2021-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Tae Ryu ,  Sang Hoon Uhm ,  Ki Seok Lee ,  Min Su Lee ,  Won Sok Lee ,  Min Hee Cho

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/24 ,  H10B12/00

CPC classification number: H01L29/7813 ,  H01L27/088 ,  H01L29/24 ,  H10B12/30

Abstract: A semiconductor memory device with improved performance by improving interface characteristics while reducing a leakage current, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line on a substrate, a first interlayer insulating layer exposing the conductive line and defining a channel trench on the substrate, a channel layer extending along a bottom and side surface of the channel trench, a first gate electrode and a second gate electrode spaced apart from each other in the channel trench, a first gate insulating layer between the channel layer and the first gate electrode, and a second gate insulating layer between the channel layer and the second gate electrode. The channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line. The first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.

公开(公告)号：US11887653B2

公开(公告)日：2024-01-30

申请号：US17705915

申请日：2022-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu Lee ,  Min Tae Ryu ,  Wonsok Lee ,  Min Hee Cho

IPC: G11C11/418 ,  G11C11/408 ,  H10B12/00

CPC classification number: G11C11/4085 ,  G11C11/4087 ,  H10B12/315

Abstract: Disclosed is a memory device including a row decoder generating word line (WL) control signals based on a row address from an external device, a first sub-array including memory cells connected to word lines, a first sub-word line driver (SWD) providing a selection voltage or a non-selection voltage to odd-numbered word lines of the word lines based on odd-numbered WL control signals corresponding to the odd-numbered word lines, and a second SWD providing the selection voltage or the non-selection voltage to even-numbered word lines of the word lines based on even-numbered WL control signals corresponding to the even-numbered word lines. The first SWD applies the non-selection voltage to non-selection word lines of the even-numbered word lines, in response to the even-numbered WL control signals, and the second SWD applies the non-selection voltage to non-selection word lines of the odd-numbered word lines, in response to the odd-numbered WL control signals.