公开(公告)号：US11282833B2

公开(公告)日：2022-03-22

申请号：US16660976

申请日：2019-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Jin Lee ,  Ji Young Kim ,  Bong Soo Kim ,  Hyeon Kyun Noh ,  Moon Young Jeong

IPC: H01L27/06 ,  H01L27/108 ,  H01L27/12 ,  H01L29/22

Abstract: A semiconductor device is provided. The semiconductor device includes a first substrate, an active region defined by an isolation film in the first substrate, an oxide semiconductor layer on the first substrate in the active region, and not comprising silicon, a recess inside the oxide semiconductor layer, and a gate structure filling the recess, comprising a gate electrode and a capping film on the gate electrode, and having an upper surface on a same plane as an upper surface of the active region.

公开(公告)号：US20180301456A1

公开(公告)日：2018-10-18

申请号：US15821089

申请日：2017-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Hee Cho ,  Jun Soo Kim ,  Hui Jung Kim ,  Tae Yoon An ,  Satoru Yamada ,  Won Sok Lee ,  Nam Ho Jeon ,  Moon Young Jeong ,  Ki Jae Hur ,  Jae Ho Hong

IPC: H01L27/108 ,  H01L27/12

CPC classification number: H01L27/10802 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10876 ,  H01L27/1207 ,  H01L29/4236

Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.

公开(公告)号：US20240292602A1

公开(公告)日：2024-08-29

申请号：US18462614

申请日：2023-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Ho Lee ,  Moon Young Jeong ,  Dong Soo Woo ,  Yoon Gi Hong

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/488

Abstract: A semiconductor memory device includes a bit line extended in a first direction on a substrate, a first word line extended in a second direction on the bit line, a second word line extended in the second direction on the bit line and spaced apart from the first word line in the first direction, a back gate electrode between the first word line and the second word line and extended in the second direction, a first active pattern between the first word line and the back gate electrode on the bit line, and a second active pattern between the first word line and the back gate electrode on the bit.

公开(公告)号：US10770463B2

公开(公告)日：2020-09-08

申请号：US16437784

申请日：2019-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Hee Cho ,  Jun Soo Kim ,  Hui Jung Kim ,  Tae Yoon An ,  Satoru Yamada ,  Won Sok Lee ,  Nam Ho Jeon ,  Moon Young Jeong ,  Ki Jae Hur ,  Jae Ho Hong

IPC: H01L27/108 ,  H01L27/12 ,  H01L21/84 ,  H01L29/423 ,  H01L21/768

Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.

公开(公告)号：US10361205B2

公开(公告)日：2019-07-23

申请号：US15821089

申请日：2017-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Hee Cho ,  Jun Soo Kim ,  Hui Jung Kim ,  Tae Yoon An ,  Satoru Yamada ,  Won Sok Lee ,  Nam Ho Jeon ,  Moon Young Jeong ,  Ki Jae Hur ,  Jae Ho Hong

IPC: H01L27/108 ,  H01L27/12 ,  H01L21/768 ,  H01L29/423

Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.