公开(公告)号：US20220085064A1

公开(公告)日：2022-03-17

申请号：US17225493

申请日：2021-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jesuk MOON ,  Juyoung LIM ,  Jongsoo KIM ,  Sunil SHIM ,  Haemin LEE ,  Wonseok CHO

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11565 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/1157

Abstract: A vertical memory device includes a gate electrode structure on a substrate, a channel extending through the gate electrode structure, and an etch stop layer on a sidewall of the gate electrode structure. The gate electrode structure includes gate electrodes spaced apart from each other in a first direction and stacked in a staircase shape. The channel includes a first portion and a second portion contacting the first portion. A lower surface of the second portion has a width less than a width of an upper surface of the first portion. The etch stop layer contacts at least one gate electrode of the gate electrodes, and overlaps an upper portion of the first portion of the channel in a horizontal direction. The at least one gate electrode contacting the etch stop layer is a dummy gate electrode including an insulating material.

公开(公告)号：US20220093638A1

公开(公告)日：2022-03-24

申请号：US17339129

申请日：2021-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyeon JUNG ,  Kwanyong KIM ,  Haemin LEE ,  Juyoung LIM ,  Wonseok CHO

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573

Abstract: A semiconductor memory device includes a substrate having a first region, a second region, and a third region main separation regions extending in the first direction and apart from each other in a second direction, first auxiliary separation regions extending in the first direction and spaced apart from each other in the second direction, and second auxiliary separation regions extending in the first direction and spaced apart from each other in the second direction. The first auxiliary separation regions are at a first pitch in the second direction between the main separation regions, the second auxiliary separation regions are disposed at a second pitch, smaller than the first pitch in the second direction between the main separation regions, and the first auxiliary separation regions and the second auxiliary separation regions are shifted from each other in the second direction.

公开(公告)号：US20210399008A1

公开(公告)日：2021-12-23

申请号：US17154159

申请日：2021-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Young LIM ,  Jongsoo KIM ,  Jesuk MOON ,  Dongwoo KIM ,  Sunil SHIM ,  Wonseok CHO

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11573 ,  H01L27/11526

Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, the electrodes including pad portions on the connection region, respectively, and the pad portions of the electrodes being stacked in a staircase structure, first vertical structures penetrating the electrode structure on the cell array region, and second vertical structures penetrating the electrode structure on the connection region, each of the second vertical structures including first parts spaced apart from each other in a first direction, and at least one second part connecting the first parts to each other, the at least one second part penetrating sidewalls of the pad portions, respectively.

公开(公告)号：US20240341100A1

公开(公告)日：2024-10-10

申请号：US18386429

申请日：2023-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jimin LEE ,  Jungtae SUNG ,  Sunil SHIM ,  Yunsun JANG ,  Wonseok CHO ,  Moorym CHOI ,  Chulmin CHOI

IPC: H10B43/50 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/50 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes gate electrode structures, a first division pattern, a second division pattern, and a memory channel structure. Each gate electrode structure includes gate electrodes spaced apart from each other on a substrate in a first direction substantially perpendicular to an upper surface of the substrate. Each gate electrode extends in a second direction substantially parallel to the upper surface of the substrate. The gate electrode structures are spaced apart from each other in a third direction substantially parallel to the upper surface and crossing the second direction. The first division pattern extends in the second direction between the gate electrode structures on the substrate. The second division pattern extends in the third direction on the substrate, and is on sidewalls of end portions in the second direction of the gate electrode structures. The memory channel structure extends in the first direction through each gate electrode structure.

公开(公告)号：US20220115397A1

公开(公告)日：2022-04-14

申请号：US17377869

申请日：2021-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonseok CHO ,  Seulbi LEE

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L25/18 ,  H01L25/065 ,  H01L21/762

Abstract: A semiconductor device including a substrate; a horizontal conductive layer disposed on the substrate; a support layer disposed on the horizontal conductive layer; a stack structure including a plurality of gate electrodes, stacked to be spaced apart from each other in a direction perpendicular to an upper surface of the support layer, and a plurality of interlayer insulating layers stacked alternately with the plurality of gate electrodes; a channel structure penetrating through the stack structure; a separation structure penetrating through the horizontal conductive layer, the support layer, and the stack structure and extending in a first direction; and a conductive pattern disposed on a level between the horizontal conductive layer and a lowermost interlayer insulating layer, among the plurality of interlayer insulating layers, and protruding outwardly of the separation structure from a side surface of the separation structure.

公开(公告)号：US20220246537A1

公开(公告)日：2022-08-04

申请号：US17529941

申请日：2021-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongsoo KIM ,  Juyoung LIM ,  Sunil SHIM ,  Wonseok CHO

IPC: H01L23/544 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: An integrated circuit device comprising a base structure, a gate stack on the base structure and comprising a plurality of gate electrodes spaced apart from each other, a first upper insulating layer on the gate stack, a plurality of channel structures that penetrate the gate stack, each of the plurality of channel structures comprises a respective alignment key protruding from the gate stack, a second upper insulating layer that overlaps the respective alignment key of each of the plurality of channel structures, a top supporting layer on the second upper insulating layer, a bit line on the top supporting layer, and a plurality of bit line contacts that electrically connect respective ones of the plurality of channel structures to the bit line. A sidewall of the first upper insulating layer includes a first step.