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    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    2.
    发明公开
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20230320096A1

    公开(公告)日：2023-10-05

    申请号：US18076090

    申请日：2022-12-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Moorym CHOI ,  Jungtae SUNG ,  Yunsun JANG

    IPC: H01L27/11582 ,  H01L27/11573

    CPC classification number: H01L27/11582 ,  H01L27/11573

    Abstract: A three-dimensional semiconductor memory device includes a substrate, a peripheral circuit structure provided on the substrate, and a cell array structure provided on the peripheral circuit structure. The cell array structure includes a stack including alternating interlayer insulating layers and conductive patterns, the conductive patterns including gate electrodes and a first source conductive pattern that is an uppermost pattern of the conductive patterns, a second source conductive pattern provided on the stack and in contact with a top surface of the first source conductive pattern, the second source conductive pattern including a material different from a material of the first source conductive pattern, and vertical channel structures provided to penetrate the stack and to be inserted into a lower portion of the second source conductive pattern. The vertical channel structures include vertical semiconductor patterns connected to the second source conductive pattern.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
    3.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20220375888A1

    公开(公告)日：2022-11-24

    申请号：US17545117

    申请日：2021-12-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Moorym CHOI ,  Yoonjo HWANG

    IPC: H01L23/00 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/065 ,  H01L25/18

    Abstract: A three-dimensional semiconductor memory device includes a first substrate, a peripheral circuit structure on the first substrate, a cell array structure on the peripheral circuit structure, the cell array structure including a stack structure having alternating interlayer dielectric layers and gate electrodes, a first insulating layer covering the stack structure, and a second substrate on the stack structure and the first insulating layer, the stack structure being between a bottom surface of the second substrate and the peripheral circuit structure, a second insulating layer on the cell array structure, a first penetration contact penetrating the first insulating layer, the second substrate, and the second insulating layer, and a second penetration contact penetrating the first insulating layer and the second insulating layer, the second penetration contact being spaced apart from the second substrate, and the first and second penetration contacts having widths decreasing with increasing distance from the first substrate.

    SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20220285302A1

    公开(公告)日：2022-09-08

    申请号：US17543250

    申请日：2021-12-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Moorym CHOI ,  Jungtae SUNG ,  Junyoung CHOI

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

    Abstract: A semiconductor device includes a first semiconductor structure including a first substrate, circuit devices on the first substrate, a lower interconnection structure on the circuit devices, and a lower bonding structure electrically connected to the lower interconnection structure, and a second semiconductor structure including a second substrate disposed on the first semiconductor structure, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to a lower surface of the second substrate, channel structures that penetrate the gate electrodes and extend in the first direction, and an upper bonding structure electrically connected to the gate electrodes and the channel structures and bonded to the lower bonding structure. The second semiconductor structure further includes a first via connected to an upper portion of the second substrate, a second via spaced apart from the first via and the second substrate, and a contact plug.

    NON-VOLATILE MEMORY DEVICE, METHOD OF MANUFACTURING THE SAME, AND MEMORY SYSTEM INCLUDING THE SAME
    5.
    发明申请
    NON-VOLATILE MEMORY DEVICE, METHOD OF MANUFACTURING THE SAME, AND MEMORY SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20230117267A1

    公开(公告)日：2023-04-20

    申请号：US17825076

    申请日：2022-05-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Moorym CHOI ,  Yunsun JANG

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

    Abstract: Provided is a non-volatile memory device including a first structure including a first substrate; a peripheral circuit; a first insulation structure; a plurality of first bonding pads; and a first interconnect structure; a second structure, which includes a conductive etch stop layer; a common source line layer; a stacked structure including alternately stacked gate layers and interlayer insulation layers; a plurality of channel structures penetrating through a cell region of the stacked structure; a second insulation structure; a plurality of second bonding pads; and a second interconnect structure and bonded to the first structure; and a connection layer including a third insulation structure; an input/output via; and an input/output pad, wherein an interface between the second insulation structure and the third insulation structure is disposed at a vertical level between the top surface and the bottom surface of the conductive etch stop layer.

    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20220216226A1

    公开(公告)日：2022-07-07

    申请号：US17497200

    申请日：2021-10-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Moorym CHOI ,  Taemok GWON ,  Junhyoung KIM ,  Hyunjae KIM ,  Youngbum WOO ,  Jongin YUN

    IPC: H01L27/11556 ,  H01L23/538 ,  H01L27/11582 ,  G11C5/06 ,  H01L29/06

    Abstract: A semiconductor device includes a first substrate including an impurity region including impurities of a first conductivity type, circuit devices on the first substrate, a lower interconnection structure electrically connected to the circuit devices, a second substrate on the lower interconnection structure and including semiconductor of the first conductivity type, gate electrodes on the second substrate and stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate, channel structures penetrating the gate electrodes, and a connection structure. The channel structures may extend perpendicular to the second substrate. The channel structures may include a channel layer. The connection structure may connect the impurity region of the first substrate to the second substrate, and the connection structure may include a via including a semiconductor of a second conductivity type.

    NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM COMPRISING THE SAME
    7.
    发明申请
    NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM COMPRISING THE SAME 有权

    公开(公告)号：US20220173119A1

    公开(公告)日：2022-06-02

    申请号：US17368029

    申请日：2021-07-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Moorym CHOI ,  Jungtae SUNG ,  Sanghee YOON ,  Wooyong JEON ,  Junyoung CHOI ,  Yoonjo HWANG

    IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/108

    Abstract: A nonvolatile memory device includes a first structure and a second structure bonded to the first structure. The second structure includes a low-resistance conductive layer, a common source line layer on the low-resistance conductive layer, a stack structure above the common source line layer, a plurality of channel structures passing through a cell region of the stack structure and contacting the common source line layer, a dummy channel structure passing through a step region of the stack structure and contacting the common source line layer, a second insulating structure on the stack structure, a plurality of second bonding pads on the second insulating structure, and a second interconnect structure in the second insulating structure.

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