公开(公告)号：US20220246537A1

公开(公告)日：2022-08-04

申请号：US17529941

申请日：2021-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongsoo KIM ,  Juyoung LIM ,  Sunil SHIM ,  Wonseok CHO

IPC: H01L23/544 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: An integrated circuit device comprising a base structure, a gate stack on the base structure and comprising a plurality of gate electrodes spaced apart from each other, a first upper insulating layer on the gate stack, a plurality of channel structures that penetrate the gate stack, each of the plurality of channel structures comprises a respective alignment key protruding from the gate stack, a second upper insulating layer that overlaps the respective alignment key of each of the plurality of channel structures, a top supporting layer on the second upper insulating layer, a bit line on the top supporting layer, and a plurality of bit line contacts that electrically connect respective ones of the plurality of channel structures to the bit line. A sidewall of the first upper insulating layer includes a first step.

公开(公告)号：US20230246395A1

公开(公告)日：2023-08-03

申请号：US18295467

申请日：2023-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoung LIM ,  Hyunwook NOH ,  Yongjae SONG ,  Inha LEE

IPC: H01R13/6582 ,  H01R12/71 ,  H01R12/79 ,  H01R13/6585

CPC classification number: H01R13/6582 ,  H01R12/716 ,  H01R12/79 ,  H01R13/6585 ,  H01R2201/00

Abstract: An electronic device is provided. The electronic device includes a housing, a first substrate arranged in an inner space of the housing and including at least one electrical element, at least one receptacle including a plurality of conductive terminals arranged to at least partially surround the at least one electrical element included in the first substrate, and at least one connector detachably coupled to the at least one receptacle and including a plurality of connector terminals, wherein at least one of the plurality of conductive terminals may be electrically connected to the ground of the first substrate.

公开(公告)号：US20220085064A1

公开(公告)日：2022-03-17

申请号：US17225493

申请日：2021-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jesuk MOON ,  Juyoung LIM ,  Jongsoo KIM ,  Sunil SHIM ,  Haemin LEE ,  Wonseok CHO

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11565 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/1157

Abstract: A vertical memory device includes a gate electrode structure on a substrate, a channel extending through the gate electrode structure, and an etch stop layer on a sidewall of the gate electrode structure. The gate electrode structure includes gate electrodes spaced apart from each other in a first direction and stacked in a staircase shape. The channel includes a first portion and a second portion contacting the first portion. A lower surface of the second portion has a width less than a width of an upper surface of the first portion. The etch stop layer contacts at least one gate electrode of the gate electrodes, and overlaps an upper portion of the first portion of the channel in a horizontal direction. The at least one gate electrode contacting the etch stop layer is a dummy gate electrode including an insulating material.

公开(公告)号：US20220310515A1

公开(公告)日：2022-09-29

申请号：US17701097

申请日：2022-03-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeshin LEE ,  Sunil SHIM ,  Juyoung LIM

IPC: H01L23/535 ,  H01L23/532 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor device includes a structure including a stack structure including a first stack structure and a second stack structure on the first stack structure; a memory vertical structure penetrating the structure; a support vertical structure including a portion penetrating the structure and including an air gap; and a peripheral contact plug, wherein the first and second stack structures includes interlayer insulating layers and gate layers alternately stacked, a side of the memory vertical structure includes a slope changing portion, the peripheral contact plug includes an upper region disposed on a level higher than an upper surface of an uppermost gate layer, the upper region of the peripheral contact plug includes a first region, a second region and a connection region between the first and second regions, and the connection region has a slope different from a slope of at least one of the first and second regions.

公开(公告)号：US20220093638A1

公开(公告)日：2022-03-24

申请号：US17339129

申请日：2021-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyeon JUNG ,  Kwanyong KIM ,  Haemin LEE ,  Juyoung LIM ,  Wonseok CHO

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573

Abstract: A semiconductor memory device includes a substrate having a first region, a second region, and a third region main separation regions extending in the first direction and apart from each other in a second direction, first auxiliary separation regions extending in the first direction and spaced apart from each other in the second direction, and second auxiliary separation regions extending in the first direction and spaced apart from each other in the second direction. The first auxiliary separation regions are at a first pitch in the second direction between the main separation regions, the second auxiliary separation regions are disposed at a second pitch, smaller than the first pitch in the second direction between the main separation regions, and the first auxiliary separation regions and the second auxiliary separation regions are shifted from each other in the second direction.

公开(公告)号：US20210089074A1

公开(公告)日：2021-03-25

申请号：US16971049

申请日：2019-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minwoo SONG ,  Younghyun BAN ,  Juyoung LIM ,  Chulmin LEE

IPC: G06F1/10 ,  G06F1/06 ,  H03K5/00

Abstract: Disclosed are an integrated circuit for controlling function modules to a low-power status depending on an operating status, an electronic device, and a control method thereof. An integrated circuit includes at least one clock generator, a clock distribution circuit that distributes a clock generated by the at least one clock generator, a plurality of function modules that receive the clock distributed by the clock distribution circuit, a monitoring circuit that monitors operating statuses of the at least one clock generator and the clock distribution circuit, a memory, and at least one control circuit. When the operating statuses of the at least one clock generator and the clock distribution circuit monitored by the monitoring circuit correspond to a specified operating status, the at least one control circuit is configured to control at least one of at least one function module of the plurality of function modules, the at least one clock generator, or the clock distribution circuit based on a specified control method. Moreover, various embodiment found through the disclosure are possible.

公开(公告)号：US20210066344A1

公开(公告)日：2021-03-04

申请号：US16850244

申请日：2020-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younghwan SON ,  Seungwon LEE ,  Seogoo KANG ,  Juyoung LIM ,  Jeehoon HAN

IPC: H01L27/11582 ,  H01L29/51 ,  H01L29/49 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11565 ,  G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G11C11/56

Abstract: A vertical non-volatile memory device includes a channel on a substrate and extending in a first direction perpendicular to an upper surface of the substrate, a first charge storage structure on an outer sidewall of the channel, a second charge storage structure on an inner sidewall of the channel, first gate electrodes spaced apart from each other in the first direction on the substrate, each which surrounds the first charge storage structure, and a second gate electrode on an inner sidewall of the second charge storage structure.