公开(公告)号：US20220093638A1

公开(公告)日：2022-03-24

申请号：US17339129

申请日：2021-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyeon JUNG ,  Kwanyong KIM ,  Haemin LEE ,  Juyoung LIM ,  Wonseok CHO

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573

Abstract: A semiconductor memory device includes a substrate having a first region, a second region, and a third region main separation regions extending in the first direction and apart from each other in a second direction, first auxiliary separation regions extending in the first direction and spaced apart from each other in the second direction, and second auxiliary separation regions extending in the first direction and spaced apart from each other in the second direction. The first auxiliary separation regions are at a first pitch in the second direction between the main separation regions, the second auxiliary separation regions are disposed at a second pitch, smaller than the first pitch in the second direction between the main separation regions, and the first auxiliary separation regions and the second auxiliary separation regions are shifted from each other in the second direction.

公开(公告)号：US20210408040A1

公开(公告)日：2021-12-30

申请号：US17473006

申请日：2021-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhwan KANG ,  Younghwan SON ,  Haemin LEE ,  Kohji KANAMORI ,  Jeehoon HAN

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11556

Abstract: A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.

公开(公告)号：US20210035987A1

公开(公告)日：2021-02-04

申请号：US16844234

申请日：2020-04-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haemin LEE ,  Jongwon KIM ,  Shinhwan KANG ,  Kohji KANAMORI ,  Jeehoon HAN

IPC: H01L27/1157 ,  H01L27/11578 ,  H01L27/11521 ,  H01L27/11556

Abstract: A semiconductor device includes a first stack group having first interlayer insulating layers and first gate layers, alternately and repeatedly stacked on a substrate and a second stack group comprising second interlayer insulating layers and second gate layers, alternately and repeatedly stacked on the first stack group. Separation structures pass through the first and second stack groups and include a first separation region and a second separation region. A vertical structure passes through the first and second stack groups and includes a first vertical region and a second vertical region. A conductive line is electrically connected to the vertical structure on the second stack group. A distance between an upper end of the first vertical region and an upper surface of the substrate is greater than a distance between an upper end of the first separation region and an upper surface of the substrate.

公开(公告)号：US20230058328A1

公开(公告)日：2023-02-23

申请号：US17739583

申请日：2022-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haemin LEE ,  Byoung-Taek KIM ,  Hyeonjoo SONG

IPC: H01L23/535 ,  H01L27/11582 ,  H01L27/11573

Abstract: Disclosed are three-dimensional (3D) semiconductor memory devices and electronic system including the same. The 3D semiconductor memory device may include a substrate including first and second regions, a stack structure including interlayer dielectric layers and gate electrodes alternately and repeatedly stacked on the substrate and having a stepwise structure on the second region, a mold structure adjacent to the stack structure on the first region and including interlayer dielectric layers and sacrificial layers alternately and repeatedly stacked on the substrate, a first separation structure crossing the stack structure and extending along a first direction from the first region toward the second region, and a second separation structure crossing the mold structure and extending in the first direction on the first region. A level of a top surface of the first separation structure may be higher than a level of a top surface of the second separation structure.

公开(公告)号：US20220310801A1

公开(公告)日：2022-09-29

申请号：US17530651

申请日：2021-11-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeonjoo SONG ,  Byoungtaek KIM ,  Haemin LEE

IPC: H01L29/40 ,  H01L27/11582 ,  H01L23/48

Abstract: A semiconductor device includes a substrate, gate electrodes stacked in a first direction, channel structures penetrating through the gate electrodes, a horizontal conductive layer below the gate electrodes on the substrate, separation regions penetrating through the gate electrodes and the horizontal conductive layer, and extending in the first and second directions, a cell region insulating layer covering the gate electrodes, and an upper support layer on the separation regions and the cell region insulating layer and having openings to overlap the separation regions. Each of the separation regions includes a contact conductive layer and a first separation insulating layer in a trench, and has first regions below the openings and second regions alternating with the first regions. The contact conductive layer is in contact with the substrate in the first regions, and is spaced apart from the substrate by the first separation insulating layer in the second regions.

公开(公告)号：US20240224521A1

公开(公告)日：2024-07-04

申请号：US18428264

申请日：2024-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhwan KANG ,  Younghwan SON ,  Haemin LEE ,  Kohji KANAMORI ,  Jeehoon HAN

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/35

Abstract: A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.

公开(公告)号：US20220415909A1

公开(公告)日：2022-12-29

申请号：US17903315

申请日：2022-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haemin LEE ,  Jongwon KIM ,  Shinhwan KANG ,  Kohji KANAMORI ,  Jeehoon HAN

IPC: H01L27/1157 ,  H01L27/11578 ,  H01L27/11521 ,  H01L27/11556

Abstract: A semiconductor device includes a first stack group having first interlayer insulating layers and first gate layers, alternately and repeatedly stacked on a substrate and a second stack group comprising second interlayer insulating layers and second gate layers, alternately and repeatedly stacked on the first stack group. Separation structures pass through the first and second stack groups and include a first separation region and a second separation region. A vertical structure passes through the first and second stack groups and includes a first vertical region and a second vertical region. A conductive line is electrically connected to the vertical structure on the second stack group. A distance between an upper end of the first vertical region and an upper surface of the substrate is greater than a distance between an upper end of the first separation region and an upper surface of the substrate.

公开(公告)号：US20220157726A1

公开(公告)日：2022-05-19

申请号：US17391445

申请日：2021-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haemin LEE

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: A 3D semiconductor memory device includes a peripheral circuit structure, an intermediate insulating layer and a cell array structure. The cell array structure includes a first substrate including a cell array region and a connection region; a stack structure comprising electrode layers and electrode interlayer insulating layers alternately stacked on the first substrate; a planarization insulating layer covering an end portion of the stack structure on the connection region; and a first through-via penetrating the planarization insulating layer, the first substrate and the intermediate insulating layer. The first through-via connects one of the electrode layers to the peripheral circuit structure. The first through-via includes a first and second via portion integrally connected to each other. The first via portion penetrates the planarization insulating layer and has a first width. The second via portion penetrates the intermediate insulating layer and has a second width greater than the first width.

公开(公告)号：US20220085064A1

公开(公告)日：2022-03-17

申请号：US17225493

申请日：2021-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jesuk MOON ,  Juyoung LIM ,  Jongsoo KIM ,  Sunil SHIM ,  Haemin LEE ,  Wonseok CHO

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11565 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/1157

Abstract: A vertical memory device includes a gate electrode structure on a substrate, a channel extending through the gate electrode structure, and an etch stop layer on a sidewall of the gate electrode structure. The gate electrode structure includes gate electrodes spaced apart from each other in a first direction and stacked in a staircase shape. The channel includes a first portion and a second portion contacting the first portion. A lower surface of the second portion has a width less than a width of an upper surface of the first portion. The etch stop layer contacts at least one gate electrode of the gate electrodes, and overlaps an upper portion of the first portion of the channel in a horizontal direction. The at least one gate electrode contacting the etch stop layer is a dummy gate electrode including an insulating material.

公开(公告)号：US20200343259A1

公开(公告)日：2020-10-29

申请号：US16562919

申请日：2019-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhwan KANG ,  Younghwan SON ,  Haemin LEE ,  Kohji KANAMORI ,  Jeehoon HAN

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11565

Abstract: A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.