公开(公告)号：US20230180472A1

公开(公告)日：2023-06-08

申请号：US18097592

申请日：2023-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung-Hee KIM ,  Woo Choel NOH ,  Ik Soo KIM ,  Jun Kwan KIM ,  Jinsub KIM ,  Yongjin SHIN

IPC: H10B41/46 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/20 ,  H10B43/40

CPC classification number: H10B41/46 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/20 ,  H10B43/40

Abstract: A semiconductor device including a substrate that includes a cell array region and a peripheral circuit region; a cell transistor on the cell array region of the substrate; a peripheral transistor on the peripheral circuit region of the substrate; a first interconnection layer connected to the cell transistor; a second interconnection layer connected to the peripheral transistor; an interlayer dielectric layer covering the first interconnection layer; and a blocking layer spaced apart from the first interconnection layer, the blocking layer covering a top surface and a sidewall of the second interconnection layer.

公开(公告)号：US20210375877A1

公开(公告)日：2021-12-02

申请号：US17165539

申请日：2021-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Sub KIM ,  Jun Kwan KIM ,  Woo Choel NOH ,  Kyoung-Hee KIM ,  Ik Soo KIM ,  Yong Jin SHIN

IPC: H01L27/108

Abstract: A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric film extending on the lower electrode along a side surface of the lower electrode that is perpendicular to the substrate, an upper electrode on the capacitor dielectric film, an interface layer including a hydrogen blocking film and a hydrogen bypass film on the upper electrode, the hydrogen blocking film including a conductive material, and a contact plug penetrating the interface layer and electrically connected to the upper electrode.

公开(公告)号：US20250149452A1

公开(公告)日：2025-05-08

申请号：US19008197

申请日：2025-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinsub KIM ,  Kyoung-hee KIM ,  Munjun KIM ,  Jun Kwan KIM ,  Woo Choel NOH

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H10B12/00

Abstract: A semiconductor device includes a substrate including a cell array region and a peripheral circuit region, capacitors on the cell array region of the substrate, peripheral transistors on the peripheral circuit region of the substrate, a first upper interlayer insulating layer on the capacitors and the peripheral transistors, a first upper contact electrically connected to at least one of the peripheral transistors, the first upper contact penetrating the first upper interlayer insulating layer, a first upper interconnection line provided on the first upper interlayer insulating layer and electrically connected to the first upper contact, a second upper interlayer insulating layer covering the first upper interconnection line, and a first blocking layer between the first upper interlayer insulating layer and the second upper interlayer insulating layer. The first blocking layer is absent between the first upper interconnection line and the first upper interlayer insulating layer.

公开(公告)号：US20210375896A1

公开(公告)日：2021-12-02

申请号：US17099994

申请日：2020-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung-Hee KIM ,  Woo Choel NOH ,  Ik Soo KIM ,  Jun Kwan KIM ,  Jinsub KIM ,  Yongjin SHIN

IPC: H01L27/11539 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11578

Abstract: A semiconductor device including a substrate that includes a cell array region and a peripheral circuit region; a cell transistor on the cell array region of the substrate; a peripheral transistor on the peripheral circuit region of the substrate; a first interconnection layer connected to the cell transistor; a second interconnection layer connected to the peripheral transistor; an interlayer dielectric layer covering the first interconnection layer; and a blocking layer spaced apart from the first interconnection layer, the blocking layer covering a top surface and a sidewall of the second interconnection layer.