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    SEMICONDUCTOR PACKAGE
    1.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20240030185A1

    公开(公告)日：2024-01-25

    申请号：US18112107

    申请日：2023-02-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JU-YOUN CHOI ,  Seunggeol RYU ,  YUN SEOK CHOI

    IPC: H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538

    CPC classification number: H01L25/0652 ,  H01L23/49816 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5389 ,  H01L23/5386

    Abstract: A semiconductor package comprising a main semiconductor chip having a first thickness, at least one semiconductor device on one side of the main semiconductor chip and having a second thickness less than the first thickness, a first molding layer that covers the main semiconductor chip and the semiconductor device so as to expose a top surface of the semiconductor device and to expose a top surface and a portion of a lateral surface of the main semiconductor chip, a first redistribution substrate below the first molding layer, a second redistribution substrate on the first molding layer, and a mold via that penetrates the first molding layer and connects the first redistribution substrate to the second redistribution substrate.

    IMAGE ENCODER, AN IMAGE SENSING DEVICE, AND AN OPERATING METHOD OF THE IMAGE ENCODER
    2.
    发明申请
    IMAGE ENCODER, AN IMAGE SENSING DEVICE, AND AN OPERATING METHOD OF THE IMAGE ENCODER 有权

    公开(公告)号：US20210344869A1

    公开(公告)日：2021-11-04

    申请号：US17129131

    申请日：2020-12-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： WON SEOK LEE ,  SEONG WOOK SONG ,  YUN SEOK CHOI

    IPC: H04N5/917 ,  H04N19/14 ,  H04N5/232

    Abstract: The present disclosure provides an image encoder. The image encoder is configured to encode an original image and reduce compression loss. The image encoder comprises an image signal processor and a compressor. The image signal processor is configured to receive a first frame image and a second frame image and generates a compressed image of the second frame image using a boundary pixel image of the first frame image. The image signal processor may include memory configured to store first reference pixel data which is the first frame image. The compressor is configured to receive the first reference pixel data from the memory and generate a bitstream obtained by encoding the second frame image based on a difference value between the first reference pixel data and the second frame image. The image signal processor generates a compressed image of the second frame image using the bitstream generated by the compressor.

    SEMICONDUCTOR PACKAGE
    3.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220013447A1

    公开(公告)日：2022-01-13

    申请号：US17181116

    申请日：2021-02-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： YUN SEOK CHOI

    IPC: H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L21/48

    Abstract: A semiconductor package includes an upper substrate having a first surface and a second surface which are opposite to each other, a semiconductor chip on the first surface of the upper substrate, a buffer layer on the second surface of the upper substrate, a mold layer between the second surface of the upper substrate and the buffer layer, a plurality of through-electrodes penetrating the upper substrate and the mold layer, an interconnection layer between the first surface of the upper substrate and the semiconductor chip and configured to electrically connect the semiconductor chip to the plurality of through-electrodes, and a plurality of bumps disposed on the buffer layer, spaced apart from the mold layer, and electrically connected to the plurality of through-electrodes. The mold layer includes an insulating material of which a coefficient of thermal expansion is greater than that of the upper substrate.

    SEMICONDUCTOR PACKAGE INCLUDING A THERMAL PILLAR AND HEAT TRANSFER FILM
    6.
    发明申请
    SEMICONDUCTOR PACKAGE INCLUDING A THERMAL PILLAR AND HEAT TRANSFER FILM 审中-公开

    公开(公告)号：US20200335480A1

    公开(公告)日：2020-10-22

    申请号：US16724592

    申请日：2019-12-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： HEEJUNG HWANG ,  JAE CHOON KIM ,  YUN SEOK CHOI

    IPC: H01L25/065 ,  H01L23/367

    Abstract: A semiconductor package includes: a first thermal pillar disposed on a package substrate, and having an opening; a first chip stack disposed on the package substrate and in the opening of the first thermal pillar, and including a first lateral surface; a semiconductor chip disposed on the package substrate and in the opening, wherein the semiconductor chip is spaced apart from the first chip stack; and a first heat transfer film disposed between the first thermal pillar and the first lateral surface of the first chip stack.

    SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
    7.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20190164942A1

    公开(公告)日：2019-05-30

    申请号：US16232159

    申请日：2018-12-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SEUNG-KWAN RYU ,  YONGHWAN KWON ,  YUN SEOK CHOI ,  CHAJEA JO ,  TAEJE CHO

    IPC: H01L25/10 ,  H01L23/31 ,  H01L23/538

    Abstract: A semiconductor package includes upper and lower semiconductor chip packages, and a redistribution wiring layer pattern interposed between the packages. The lower package includes a molding layer in which at least one chip is embedded, and has a top surface and an inclined sidewall surface along which the redistribution wiring layer pattern is formed. The upper and lower packages are electrically connected to through the redistribution wiring layer pattern. A first package may be formed by a wafer level packaging technique and may include a redistribution wiring layer as a substrate, a semiconductor chip disposed on the redistribution wiring layer, and a molding layer on which the lower package, redistribution wiring layer pattern and upper package are disposed.

    SEMICONDUCTOR PACKAGE
    8.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230111854A1

    公开(公告)日：2023-04-13

    申请号：US17851245

    申请日：2022-06-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JU-IL CHOI ,  UN-BYOUNG KANG ,  MINSEUNG YOON ,  YONGHOE CHO ,  JEONGGI JIN ,  YUN SEOK CHOI

    IPC: H01L25/10 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48

    Abstract: Provided is a semiconductor package, including a first redistribution substrate, a first semiconductor chip on the first redistribution substrate, first bumps between the first redistribution substrate and the first semiconductor chip, a conductive structure on the first redistribution substrate and spaced apart from the first semiconductor chip, a second redistribution substrate on the first semiconductor chip, second bumps between the first semiconductor chip and the second redistribution substrate, a second semiconductor chip on the second redistribution substrate, a first mold layer between the first redistribution substrate and the second redistribution substrate, and on the first semiconductor chip, and a second mold layer on the second redistribution substrate and the second semiconductor chip, and spaced apart from the first mold layer.

    SEMICONDUCTOR PACKAGE
    9.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230055812A1

    公开(公告)日：2023-02-23

    申请号：US17983018

    申请日：2022-11-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YUN SEOK CHOI

    IPC: H01L25/065 ,  H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/48

    Abstract: A semiconductor package includes an upper substrate having a first surface and a second surface which are opposite to each other, a lower semiconductor chip disposed on the first surface of the upper substrate, a plurality of conductive pillars disposed on the first surface of the upper substrate at at least one side of the lower semiconductor chip, and an upper semiconductor chip disposed on the second surface of the upper substrate. The lower semiconductor chip and the plurality of conductive pillars are connected to the first surface of the upper substrate, and the upper semiconductor chip is connected to the second surface of the upper substrate.

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