公开(公告)号：US20170083401A1

公开(公告)日：2017-03-23

申请号：US15229774

申请日：2016-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ye-sin Ryu ,  Hoi-Ju CHUNG ,  Sang-Uhn CHA ,  Young-Yong BYUN ,  Seong-Jin JANG

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1048 ,  G11C11/1677 ,  G11C29/52 ,  G11C2029/0411

Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, an error correction circuit and a first path selection circuit. The memory cell array includes a plurality of bank arrays. The control logic circuit controls access to the memory cell array and generates a density mode signal based on a command. The first path selection circuit selectively provides write data to the error correction circuit.