公开(公告)号：US20160155515A1

公开(公告)日：2016-06-02

申请号：US14817212

申请日：2015-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil SON ,  Chul-Woo PARK ,  Hoi-Ju CHUNG ,  Sang-Uhn CHA ,  Seong-Jin JANG

IPC: G11C29/44 ,  G11C29/38 ,  G11C29/42 ,  G11C11/4096

CPC classification number: G11C29/4401 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/4096 ,  G11C29/42 ,  G11C2029/4402

Abstract: A semiconductor memory device includes a memory cell array and a test circuit. The test circuit reads data stream from the memory cell array, configured to, on comparing bits of each first unit in the data stream, compares corresponding bits in the first units as each second unit and outputs a fail information signal including pass/fail information on the data stream and additional information on the data stream, in a test mode of the semiconductor memory device.

Abstract translation: 半导体存储器件包括存储单元阵列和测试电路。 测试电路从存储单元阵列读取数据流，配置为在比较数据流中的每个第一单元的比特时，将第一单元中的相应比特作为每个第二单元进行比较，并输出包括通过/失败信息的故障信息信号 数据流和关于数据流的附加信息，在半导体存储器件的测试模式中。

公开(公告)号：US20170365361A1

公开(公告)日：2017-12-21

申请号：US15696794

申请日：2017-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uhn CHA ,  Hoi-Ju CHUNG ,  Jong-Pil SON ,  Kwang-II PARK ,  Seong-Jin JANG

IPC: G11C29/52 ,  G11C29/00 ,  G06F11/10 ,  G11C29/44 ,  G11C11/15 ,  G11C29/04

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G11C11/15 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C29/702 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.

公开(公告)号：US20130100998A1

公开(公告)日：2013-04-25

申请号：US13714473

申请日：2012-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Jun BAE ,  Seong-Jin JANG ,  Beom-Sig CHO

IPC: H04L7/10

CPC classification number: G11C7/22 ,  H03K19/0966 ,  H04L7/0008 ,  H04L7/033 ,  H04L7/10

Abstract: A method of communication to a semiconductor device includes: transmitting a sampling clock signal from a first semiconductor device to a second semiconductor device; transmitting a training signal from the first semiconductor device to the second semiconductor device while transmitting of the sampling clock signal, the training signal comprising plural test patterns sent sequentially to the second semiconductor device, phases of at least some of the test patterns being adjusted to be different from each other during transmitting of the training signal; receiving first information from the second semiconductor device over a first signal line, the first signal line separate from a data bus connected between the first semiconductor device and the second semiconductor device; and transmitting a data signal over the data bus while transmitting the sampling clock signal, the data signal sent at a timing with respect to the sampling clock signal responsive to the received first information.

Abstract translation: 一种与半导体器件通信的方法包括：将采样时钟信号从第一半导体器件传输到第二半导体器件; 在将所述采样时钟信号发送的同时将训练信号从所述第一半导体器件传输到所述第二半导体器件，所述训练信号包括顺序发送到所述第二半导体器件的多个测试图案，所述至少一些所述测试图案的相位被调整为 在训练信号的发送期间彼此不同; 通过第一信号线从第二半导体器件接收第一信息，第一信号线与连接在第一半导体器件和第二半导体器件之间的数据总线分开; 并且在发送采样时钟信号的同时，通过数据总线发送数据信号，所述数据信号响应于所接收到的第一信息而相对于采样时钟信号在定时发送。

公开(公告)号：US20170083401A1

公开(公告)日：2017-03-23

申请号：US15229774

申请日：2016-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ye-sin Ryu ,  Hoi-Ju CHUNG ,  Sang-Uhn CHA ,  Young-Yong BYUN ,  Seong-Jin JANG

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1048 ,  G11C11/1677 ,  G11C29/52 ,  G11C2029/0411

Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, an error correction circuit and a first path selection circuit. The memory cell array includes a plurality of bank arrays. The control logic circuit controls access to the memory cell array and generates a density mode signal based on a command. The first path selection circuit selectively provides write data to the error correction circuit.