Abstract:
A semiconductor memory device includes a ZQ calibration unit configured to generate a pull-up VOH code according to a first target VOH proportional to a power supply voltage and an output driver configured to generate a data signal having a VOH proportional to the power supply voltage based on the pull-up VOH code, wherein VOH means “output high level voltage.”
Abstract:
A small signal receiver includes a first current adjustment circuit connected between a first power supply voltage terminal and a first node to provide current in response to a self-bias signal, a self-biased differential amplifier connected between the first node and a second node to compare an input signal with a reference voltage, provide the self-bias signal to a self-biasing node and output an output signal through an output node, and a second current adjustment circuit connected between the second node and a second power supply voltage terminal to sink current at the second node in response to the self-bias signal. The self-biased differential amplifier includes a swing stabilizing block connected between an input node to which the input signal is applied and the self-biasing node to stabilize the input signal compared with the reference voltage.
Abstract:
A small signal receiver includes a first current adjustment circuit connected between a first power supply voltage terminal and a first node to provide current in response to a self-bias signal, a self-biased differential amplifier connected between the first node and a second node to compare an input signal with a reference voltage, provide the self-bias signal to a self-biasing node and output an output signal through an output node, and a second current adjustment circuit connected between the second node and a second power supply voltage terminal to sink current at the second node in response to the self-bias signal. The self-biased differential amplifier includes a swing stabilizing block connected between an input node to which the input signal is applied and the self-biasing node to stabilize the input signal compared with the reference voltage.
Abstract:
A method of operating a memory controller includes: receiving a data signal from a memory device, wherein the data signal has an output high level voltage (VOH); determining a reference voltage according to the VOH; and comparing the data signal with the reference voltage to determine a received data value, wherein the VOH is proportional to a power supply voltage (VDDQ).
Abstract:
A semiconductor memory device includes a ZQ calibration unit configured to generate a pull-up VOH code according to a first target VOH proportional to a power supply voltage and an output driver configured to generate a data signal having a VOH proportional to the power supply voltage based on the pull-up VOH code, wherein VOH means “output high level voltage.”
Abstract:
An integrated circuit comprising an output driver including an output terminal, and a receiving circuit including a termination resistor connected between the output terminal and a ground. The output driver comprising a first NMOS transistor configured to pull up a voltage of the output terminal to a pull-up voltage in response to a pull-up signal, and a second NMOS transistor configured to pull down the output terminal to a ground voltage in response to a pull-down signal.
Abstract:
A semiconductor memory device includes a ZQ calibration unit configured to generate a pull-up VOH code according to a first target VOH proportional to a power supply voltage and an output driver configured to generate a data signal having a VOH proportional to the power supply voltage based on the pull-up VOH code, wherein VOH means “output high level voltage.”