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    SEMICONDUCTOR MEMORY DEVICES HAVING INTERNAL CLOCK SIGNALS AND MEMORY SYSTEMS INCLUDING SUCH MEMORY DEVICES
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES HAVING INTERNAL CLOCK SIGNALS AND MEMORY SYSTEMS INCLUDING SUCH MEMORY DEVICES 有权
    具有内部时钟信号和存储器系统的半导体存储器件，包括这样的存储器件

    公开(公告)号：US20130182524A1

    公开(公告)日：2013-07-18

    申请号：US13729068

    申请日：2012-12-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young Jin Jeon ,  Yoon Joo Eom ,  Young Chul Cho

    IPC: G11C8/18

    CPC classification number: G11C8/18 ,  G11C7/222 ,  G11C7/225

    Abstract: A semiconductor memory device has a clock input buffer that is turned ‘on’ or ‘off’ in response to a first control signal. The clock input buffer is configured to buffer an external clock signal in order to output a buffered clock signal. The memory device further includes an internal clock generator that is configured to generate an internal clock signal in response to the buffered clock signal. The generation of the internal clock signal is started in response to a second control signal.

    Abstract translation: 半导体存储器件具有响应于第一控制信号而被打开或关闭的时钟输入缓冲器。 时钟输入缓冲器被配置为缓冲外部时钟信号，以输出缓冲的时钟信号。 存储器件还包括内部时钟发生器，其被配置为响应于缓冲的时钟信号产生内部时钟信号。 响应于第二控制信号启动内部时钟信号的产生。

    Output driving circuit capable of decreasing noise, and semiconductor memory device including the same
    9.
    发明授权
    Output driving circuit capable of decreasing noise, and semiconductor memory device including the same 有权
    能够降低噪声的输出驱动电路和包括其的半导体存储器件

    公开(公告)号：US08917119B2

    公开(公告)日：2014-12-23

    申请号：US13747710

    申请日：2013-01-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young Chul Cho

    IPC: H03B1/00 ,  G11C7/02 ,  G11C7/10 ,  H03K17/56 ,  H03K19/0185

    CPC classification number: G11C7/02 ,  G11C7/10 ,  G11C7/1057 ,  H03K17/56 ,  H03K19/0185

    Abstract: An output driving circuit includes a first pull-up transistor, a first pull-down transistor and a second pull-down transistor. The first pull-up transistor is configured to generate a first output signal at the output node in response to a first control signal. The first pull-down transistor is configured to generate a second output signal at the output node in response to a second control signal. The second pull-down transistor is configured to connect the output node to the first ground voltage in response to a third control signal. The memory device including the output driving circuit may be insensitive to noise and may have little data transmission error.

    Abstract translation: 输出驱动电路包括第一上拉晶体管，第一下拉晶体管和第二下拉晶体管。 第一上拉晶体管被配置为响应于第一控制信号在输出节点处产生第一输出信号。 第一下拉晶体管被配置为响应于第二控制信号在输出节点处产生第二输出信号。 第二下拉晶体管被配置为响应于第三控制信号将输出节点连接到第一接地电压。 包括输出驱动电路的存储器件可能对噪声不敏感，并且可能具有很小的数据传输误差。

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