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    Small signal receiver and integrated circuit including the same
    2.
    发明授权
    Small signal receiver and integrated circuit including the same 有权
    小信号接收机和集成电路包括相同

    公开(公告)号：US09209764B2

    公开(公告)日：2015-12-08

    申请号：US13841199

    申请日：2013-03-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Young Chul Cho ,  Yong Cheol Bae ,  Yoon Joo Eom ,  Young Jin Jeon

    IPC: G11C7/10 ,  H03F3/45 ,  G11C7/06

    CPC classification number: H03F3/45179 ,  G11C7/06 ,  G11C7/10 ,  G11C7/1084 ,  H03F3/45237 ,  H03F3/45672 ,  H03F2203/45296 ,  H03F2203/45316 ,  H03F2203/45328 ,  H03F2203/45358 ,  H03F2203/45372 ,  H03F2203/45431 ,  H03F2203/45506

    Abstract: A small signal receiver includes a first current adjustment circuit connected between a first power supply voltage terminal and a first node to provide current in response to a self-bias signal, a self-biased differential amplifier connected between the first node and a second node to compare an input signal with a reference voltage, provide the self-bias signal to a self-biasing node and output an output signal through an output node, and a second current adjustment circuit connected between the second node and a second power supply voltage terminal to sink current at the second node in response to the self-bias signal. The self-biased differential amplifier includes a swing stabilizing block connected between an input node to which the input signal is applied and the self-biasing node to stabilize the input signal compared with the reference voltage.

    Abstract translation: 小信号接收机包括连接在第一电源电压端和第一节点之间以响应自偏置信号提供电流的第一电流调节电路，连接在第一节点和第二节点之间的自偏置差动放大器 将输入信号与参考电压进行比较，将自偏置信号提供给自偏压节点并通过输出节点输出输出信号，以及连接在第二节点和第二电源电压端之间的第二电流调节电路， 响应于自偏置信号在第二节点处吸收电流。 自偏置差分放大器包括连接在施加输入信号的输入节点和自偏压节点之间的摆动稳定块，以使稳定输入信号与参考电压相比较。

    Semiconductor memory devices having internal clock signals and memory systems including such memory devices
    3.
    发明授权
    Semiconductor memory devices having internal clock signals and memory systems including such memory devices 有权
    具有内部时钟信号的半导体存储器件和包括这种存储器件的存储器系统

    公开(公告)号：US08934317B2

    公开(公告)日：2015-01-13

    申请号：US13729068

    申请日：2012-12-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young Jin Jeon ,  Yoon Joo Eom ,  Young Chul Cho

    IPC: G11C7/22 ,  G11C8/18

    CPC classification number: G11C8/18 ,  G11C7/222 ,  G11C7/225

    Abstract: A semiconductor memory device has a clock input buffer that is turned ‘on’ or ‘off’ in response to a first control signal. The clock input buffer is configured to buffer an external clock signal in order to output a buffered clock signal. The memory device further includes an internal clock generator that is configured to generate an internal clock signal in response to the buffered clock signal. The generation of the internal clock signal is started in response to a second control signal.

    Abstract translation: 半导体存储器件具有响应于第一控制信号而被打开或关闭的时钟输入缓冲器。 时钟输入缓冲器被配置为缓冲外部时钟信号，以输出缓冲的时钟信号。 存储器件还包括内部时钟发生器，其被配置为响应于缓冲的时钟信号产生内部时钟信号。 响应于第二控制信号启动内部时钟信号的产生。

    SMALL SIGNAL RECEIVER AND INTEGRATED CIRCUIT INCLUDING THE SAME
    4.
    发明申请
    SMALL SIGNAL RECEIVER AND INTEGRATED CIRCUIT INCLUDING THE SAME 有权
    小信号接收器和集成电路，包括它们

    公开(公告)号：US20140003162A1

    公开(公告)日：2014-01-02

    申请号：US13841199

    申请日：2013-03-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： YOUNG CHUL CHO ,  Yong Cheol Bae ,  Yoon Joo Eom ,  Young Jin Jeon

    IPC: H03F3/45 ,  G11C7/10

    CPC classification number: H03F3/45179 ,  G11C7/06 ,  G11C7/10 ,  G11C7/1084 ,  H03F3/45237 ,  H03F3/45672 ,  H03F2203/45296 ,  H03F2203/45316 ,  H03F2203/45328 ,  H03F2203/45358 ,  H03F2203/45372 ,  H03F2203/45431 ,  H03F2203/45506

    Abstract: A small signal receiver includes a first current adjustment circuit connected between a first power supply voltage terminal and a first node to provide current in response to a self-bias signal, a self-biased differential amplifier connected between the first node and a second node to compare an input signal with a reference voltage, provide the self-bias signal to a self-biasing node and output an output signal through an output node, and a second current adjustment circuit connected between the second node and a second power supply voltage terminal to sink current at the second node in response to the self-bias signal. The self-biased differential amplifier includes a swing stabilizing block connected between an input node to which the input signal is applied and the self-biasing node to stabilize the input signal compared with the reference voltage.

    Abstract translation: 小信号接收机包括连接在第一电源电压端和第一节点之间以响应自偏置信号提供电流的第一电流调节电路，连接在第一节点和第二节点之间的自偏置差动放大器 将输入信号与参考电压进行比较，将自偏置信号提供给自偏压节点并通过输出节点输出输出信号，以及连接在第二节点和第二电源电压端之间的第二电流调节电路， 响应于自偏置信号在第二节点处吸收电流。 自偏置差分放大器包括连接在施加输入信号的输入节点和自偏压节点之间的摆动稳定块，以使稳定输入信号与参考电压相比较。

    SEMICONDUCTOR MEMORY DEVICES HAVING INTERNAL CLOCK SIGNALS AND MEMORY SYSTEMS INCLUDING SUCH MEMORY DEVICES
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES HAVING INTERNAL CLOCK SIGNALS AND MEMORY SYSTEMS INCLUDING SUCH MEMORY DEVICES 有权
    具有内部时钟信号和存储器系统的半导体存储器件，包括这样的存储器件

    公开(公告)号：US20130182524A1

    公开(公告)日：2013-07-18

    申请号：US13729068

    申请日：2012-12-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young Jin Jeon ,  Yoon Joo Eom ,  Young Chul Cho

    IPC: G11C8/18

    CPC classification number: G11C8/18 ,  G11C7/222 ,  G11C7/225

    Abstract: A semiconductor memory device has a clock input buffer that is turned ‘on’ or ‘off’ in response to a first control signal. The clock input buffer is configured to buffer an external clock signal in order to output a buffered clock signal. The memory device further includes an internal clock generator that is configured to generate an internal clock signal in response to the buffered clock signal. The generation of the internal clock signal is started in response to a second control signal.

    Abstract translation: 半导体存储器件具有响应于第一控制信号而被打开或关闭的时钟输入缓冲器。 时钟输入缓冲器被配置为缓冲外部时钟信号，以输出缓冲的时钟信号。 存储器件还包括内部时钟发生器，其被配置为响应于缓冲的时钟信号产生内部时钟信号。 响应于第二控制信号启动内部时钟信号的产生。

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