公开(公告)号：US11335431B2

公开(公告)日：2022-05-17

申请号：US17216160

申请日：2021-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Ryun Kim ,  Yoon-Na Oh ,  Hyung-Jin Kim ,  Hui-Kap Yang ,  Jang-Woo Ryu

IPC: G11C29/00 ,  G11C8/12 ,  G11C29/24 ,  G11C29/44 ,  G11C29/04

Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.

公开(公告)号：US11626185B2

公开(公告)日：2023-04-11

申请号：US17723200

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Ryun Kim ,  Yoon-Na Oh ,  Hyung-Jin Kim ,  Hui-Kap Yang ,  Jang-Woo Ryu

IPC: G11C8/12 ,  G11C29/00 ,  G11C29/24 ,  G11C29/44 ,  G11C29/04

Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.

公开(公告)号：US10971247B2

公开(公告)日：2021-04-06

申请号：US16283650

申请日：2019-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Ryun Kim ,  Yoon-Na Oh ,  Hyung-Jin Kim ,  Hui-Kap Yang ,  Jang-Woo Ryu

IPC: G11C8/12 ,  G11C29/00 ,  G11C29/24 ,  G11C29/44 ,  G11C29/04

Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.

公开(公告)号：US10204700B1

公开(公告)日：2019-02-12

申请号：US15271600

申请日：2016-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon-Na Oh ,  Deok-Gu Yoon ,  Sang-Uhn Cha

IPC: G11C29/52 ,  G06F11/07

Abstract: A memory system includes a semiconductor memory device and a test device. The semiconductor memory device includes a memory cell array, an error correction circuit and a test circuit. The test device controls a test of the semiconductor memory device, and the test device includes a first fail address memory and a second fail address memory. The test circuit performs a first test on the memory cell array to selectively record a first test result associated with the first test in the first fail address memory and performs a second test on the memory cell array to record a second test result associated with the second test in the second fail address memory. The test circuit is configured to perform the first test and the second test based on a test pattern data from the test device in a test mode.