公开(公告)号：US11626185B2

公开(公告)日：2023-04-11

申请号：US17723200

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Ryun Kim ,  Yoon-Na Oh ,  Hyung-Jin Kim ,  Hui-Kap Yang ,  Jang-Woo Ryu

IPC: G11C8/12 ,  G11C29/00 ,  G11C29/24 ,  G11C29/44 ,  G11C29/04

Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.

公开(公告)号：US10971247B2

公开(公告)日：2021-04-06

申请号：US16283650

申请日：2019-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Ryun Kim ,  Yoon-Na Oh ,  Hyung-Jin Kim ,  Hui-Kap Yang ,  Jang-Woo Ryu

IPC: G11C8/12 ,  G11C29/00 ,  G11C29/24 ,  G11C29/44 ,  G11C29/04

Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.

公开(公告)号：US09891855B2

公开(公告)日：2018-02-13

申请号：US15438651

申请日：2017-02-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hui-Kap Yang ,  Myung-Kyoon Yim ,  Soo-Hwan Kim

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0634 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G06F3/0614 ,  G06F3/0673 ,  G11C11/4074

Abstract: A memory device is provided which is capable of adjusting an operation voltage, and an application processor is provided for controlling the memory device. The memory device may include: a receiving terminal for receiving a voltage control signal from an external source, the voltage control signal being for adjusting an operation voltage level according to an operation speed of the memory device; and a voltage adjustment unit for adjusting a level of an operation voltage of the memory device in response to the voltage control signal. The level of the operation voltage is adjusted before a memory operation is performed at the operation speed corresponding to the adjusted operation voltage.

公开(公告)号：US11335431B2

公开(公告)日：2022-05-17

申请号：US17216160

申请日：2021-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Ryun Kim ,  Yoon-Na Oh ,  Hyung-Jin Kim ,  Hui-Kap Yang ,  Jang-Woo Ryu

IPC: G11C29/00 ,  G11C8/12 ,  G11C29/24 ,  G11C29/44 ,  G11C29/04

Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.

公开(公告)号：US09892779B2

公开(公告)日：2018-02-13

申请号：US15331970

申请日：2016-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Chang Kang ,  Hui-Kap Yang

IPC: G11C7/00 ,  G11C11/406 ,  G06F3/06 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G11C11/40618 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/40603 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4091

Abstract: A memory device includes a memory bank, a row selection circuit and a refresh controller. The memory bank includes a plurality of memory blocks, and each memory block includes a plurality of memory cells arranged in rows and columns. The row selection circuit performs an access operation with respect to the memory bank and a hammer refresh operation with respect to a row that is physically adjacent to a row that is accessed intensively. The refresh controller controls the row selection circuit such that the hammer refresh operation is performed during a row active time for the access operation. The hammer refresh operation may be performed efficiently and performance of the memory device may be enhanced by performing the hammer refresh operation during the row active time for the access operation.