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公开(公告)号：US11437396B2
公开(公告)日：2022-09-06
申请号：US17032128
申请日：2020-09-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Junhyoung Kim , Jisung Cheon , Yoonhwan Son , Seungmin Lee
IPC: H01L27/11578 , H01L27/11568 , H01L27/11573
Abstract: A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.
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公开(公告)号：US11276706B2
公开(公告)日：2022-03-15
申请号：US15930867
申请日：2020-05-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Geunwon Lim , Yoonhwan Son , Junyoung Choi
IPC: H01L27/11582 , H01L29/51 , H01L21/28 , H01L27/11565
Abstract: Vertical memory devices and method of manufacturing the same are disclosed. The vertical memory device includes a substrate having a cell block area, a block separation area and a boundary area, a plurality of stack structures arranged in the cell block area and the boundary area such that insulation interlayer patterns are stacked on the substrate alternately with the electrode patterns. The stack structures are spaced apart by the block separation area in the third direction. A plurality of channel structures extend through the stack structures to the substrate in the cell block area in the first direction and are connected to the substrate. A plurality of dummy channel structures extend through upper portions of each of the stack structures in the boundary area and are connected to a dummy bottom electrode pattern spaced apart from the substrate. The bridge defect is thus substantially prevented near the substrate.
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Patent Agency Ranking
公开(公告)号：US20230363157A1
公开(公告)日：2023-11-09
申请号：US18352182
申请日：2023-07-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Junhyoung Kim , Jisung Cheon , Yoonhwan Son , Seungmin Lee
Abstract: A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.
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公开(公告)号：US20230062069A1
公开(公告)日：2023-03-02
申请号：US17860800
申请日：2022-07-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yoonhwan Son , Hyeongjin Kim , Seungjun Shin , Joongshik Shin , Minsoo Shin , Jeehoon Han
IPC: G11C16/04 , H01L23/528 , H01L27/11519 , H01L27/11524 , H01L27/11526 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11582
Abstract: A semiconductor device includes a lower stepped connection part at a first vertical level on a substrate, an upper stepped connection part at a second vertical level higher than the first vertical level on the substrate, a lower insulating block contacting each of the plurality of lower conductive pad parts at the first vertical level, an upper insulating block contacting each of the plurality of upper conductive pad parts at the second vertical level, an intermediate insulating film between the lower insulating block and the upper insulating block at a third vertical level between the first and second vertical levels, and a first plug structure extending into the lower stepped connection part, the intermediate insulating film, and the upper insulating block in the vertical direction, wherein a width of the first plug structure in the horizontal direction is greatest at the third vertical level.
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公开(公告)号：US12133384B2
公开(公告)日：2024-10-29
申请号：US18352182
申请日：2023-07-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Junhyoung Kim , Jisung Cheon , Yoonhwan Son , Seungmin Lee
Abstract: A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.
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公开(公告)号：US12010852B2
公开(公告)日：2024-06-11
申请号：US17236053
申请日：2021-04-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yoonhwan Son , Gaeun Kim , Jeongseok Lee
IPC: H10B43/40 , H01L23/535 , H10B41/27 , H10B41/41 , H10B43/27
CPC classification number: H10B43/40 , H01L23/535 , H10B41/27 , H10B41/41 , H10B43/27
Abstract: A three-dimensional semiconductor memory device includes a peripheral circuit structure having peripheral circuits on a semiconductor substrate, and landing pads connected to the peripheral circuits, an electrode structure on the peripheral circuit structure, the electrode structure including vertically stacked electrodes, a planarized dielectric layer that covers the electrode structure, peripheral through plugs spaced apart from the electrode structure, the peripheral through plugs penetrating the planarized dielectric layer to connect to the landing pads, conductive lines connected through contact plugs, respectively, to the peripheral through plugs, and at least one dummy through plug adjacent to a first peripheral through plug of the peripheral through plugs, the at least one dummy through plug penetrating the planarized dielectric layer and being insulated from the conductive lines.
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公开(公告)号：US11737270B2
公开(公告)日：2023-08-22
申请号：US17897255
申请日：2022-08-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Junhyoung Kim , Jisung Cheon , Yoonhwan Son , Seungmin Lee
Abstract: A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.
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