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    METHODS OF MANUFACTURING VERTICAL MEMORY DEVICES
    2.
    发明申请
    METHODS OF MANUFACTURING VERTICAL MEMORY DEVICES 审中-公开

    公开(公告)号：US20190013330A1

    公开(公告)日：2019-01-10

    申请号：US16117036

    申请日：2018-08-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kohji KANAMORI ,  Shin-Hwan KANG ,  Young-Woo PARK ,  Jung-Hoon PARK

    IPC: H01L27/11582 ,  H01L49/02 ,  H01L29/423

    CPC classification number: H01L27/11582 ,  H01L28/00 ,  H01L29/42344

    Abstract: A vertical memory device includes insulating interlayer patterns, of gate electrodes, a channel, and a charge storage pattern structure. The insulating interlayer patterns are spaced in a first direction. The gate electrodes between are neighboring insulating interlayer patterns, respectively. The channel extends through the insulating interlayer patterns and the gate electrodes in the first direction. The charge storage pattern structure includes a tunnel insulation pattern, a charge trapping pattern structure, and a blocking pattern sequentially stacked between the channel and each of the gate electrodes in a second direction. The charge trapping pattern structure includes charge trapping patterns spaced in the first direction. The charge trapping patterns are adjacent to sidewalls of first gate electrodes, respectively. A first charge trapping pattern extends in the first direction along a sidewall of a first insulating interlayer pattern.

    SEMICONDUCTOR DEVICES
    3.
    发明申请
    SEMICONDUCTOR DEVICES 审中-公开
    半导体器件

    公开(公告)号：US20170047344A1

    公开(公告)日：2017-02-16

    申请号：US15334968

    申请日：2016-10-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Duk LEE ,  Young-Woo PARK

    IPC: H01L27/115 ,  H01L23/528 ,  H01L21/28 ,  H01L21/768 ,  H01L21/02

    CPC classification number: H01L21/02636 ,  H01L21/28282 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582

    Abstract: A semiconductor device includes a lower insulation layer, a plurality of base layer patterns separated from each other on the lower insulation layer, a separation layer pattern between the base layer patterns, a plurality of channels extending in a vertical direction with respect to top surfaces of the base layer patterns, and a plurality of gate lines surrounding outer sidewalls of the channels, being stacked in the vertical direction and spaced apart from each other.

    Abstract translation: 半导体器件包括下绝缘层，在下绝缘层上彼此分离的多个基底层图案，在基底层图案之间的分离层图案，在垂直方向上延伸的多个通道相对于 基底层图案和围绕通道的外侧壁的多条栅极线在垂直方向上堆叠并彼此间隔开。

    METHODS OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICES
    4.
    发明申请
    METHODS OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICES 审中-公开
    制造垂直半导体器件的方法

    公开(公告)号：US20140193966A1

    公开(公告)日：2014-07-10

    申请号：US14200680

    申请日：2014-03-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byung-Kwan YOU ,  Kwang-Soo SEOL ,  Young-Woo PARK ,  Jin-Soo LIM

    IPC: H01L21/28 ,  H01L21/02

    CPC classification number: H01L21/28282 ,  H01L21/02104 ,  H01L27/11582 ,  H01L29/7926

    Abstract: Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves.

    Abstract translation: 制造垂直半导体器件的方法可以包括形成包括牺牲层和绝缘夹层的模具结构，其中形成有第一开口。 牺牲层和绝缘夹层可以重复地和交替地层叠在基板上。 第一开口可能暴露基板。 可以通过氧化由第一开口暴露的牺牲层的部分来形成阻挡层。 分别可以在第一开口的侧壁上形成第一半导体层图案，电荷俘获层图案和隧道绝缘层图案。 可以在第一多晶硅层图案和第一开口的底部上形成第二半导体层。 可以部分去除牺牲层和绝缘夹层以形成第二开口。 可以去除牺牲层以在绝缘夹层之间形成凹槽。 控制栅电极可以形成在凹槽中。

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