公开(公告)号：US20140193966A1

公开(公告)日：2014-07-10

申请号：US14200680

申请日：2014-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung-Kwan YOU ,  Kwang-Soo SEOL ,  Young-Woo PARK ,  Jin-Soo LIM

IPC: H01L21/28 ,  H01L21/02

CPC classification number: H01L21/28282 ,  H01L21/02104 ,  H01L27/11582 ,  H01L29/7926

Abstract: Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves.

Abstract translation: 制造垂直半导体器件的方法可以包括形成包括牺牲层和绝缘夹层的模具结构，其中形成有第一开口。 牺牲层和绝缘夹层可以重复地和交替地层叠在基板上。 第一开口可能暴露基板。 可以通过氧化由第一开口暴露的牺牲层的部分来形成阻挡层。 分别可以在第一开口的侧壁上形成第一半导体层图案，电荷俘获层图案和隧道绝缘层图案。 可以在第一多晶硅层图案和第一开口的底部上形成第二半导体层。 可以部分去除牺牲层和绝缘夹层以形成第二开口。 可以去除牺牲层以在绝缘夹层之间形成凹槽。 控制栅电极可以形成在凹槽中。

公开(公告)号：US20190157294A1

公开(公告)日：2019-05-23

申请号：US16118647

申请日：2018-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji KANAMORI ,  Young-Hwan SON ,  Byung-Kwan YOU ,  Eun-Taek JUNG

IPC: H01L27/11582 ,  H01L21/768 ,  H01L23/532 ,  H01L21/56 ,  H01L21/764 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/565 ,  H01L21/764 ,  H01L21/76832 ,  H01L23/5329 ,  H01L27/1157 ,  H01L28/88 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/66833

Abstract: A vertical memory device includes first, second and third impurity regions sequentially stacked in a first direction substantially perpendicular to an upper surface of a substrate, a gate electrode structure including gate electrodes spaced apart from each other in the first direction on the third impurity region, a channel extending through the gate electrode structure, the second and third impurity regions, and an upper portion of the first impurity region on the substrate in the first direction, and a charge storage structure covering a portion of an outer sidewall and a lower surface of the channel. The channel directly contacts a sidewall of the second impurity region.

公开(公告)号：US20210005628A1

公开(公告)日：2021-01-07

申请号：US16933328

申请日：2020-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-Taek JUNG ,  Joong-Shik SHIN ,  Byung-Kwan YOU

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/66 ,  H01L21/311 ,  H01L29/788 ,  H01L29/792 ,  H01L27/1157

Abstract: A vertical type semiconductor device includes a substrate that has a plurality of trenches, a support pattern that fills the plurality of trenches and protrudes from a top surface of the substrate, a semiconductor layer disposed on the substrate that fills a space between the support patterns, a stacked structure disposed on the support pattern and the semiconductor layer that includes a plurality of insulation layers and a plurality of first conducive patterns that are alternately and repeatedly stacked, and a plurality of channel structures that penetrate through the structure and the semiconductor layer and that extend into the support pattern. Each channel structure includes a channel layer. At least a portion of the channel layer makes contact with the semiconductor layer.

公开(公告)号：US20130175663A1

公开(公告)日：2013-07-11

申请号：US13728785

申请日：2012-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung-Kwan YOU ,  Seung-Woo PAEK ,  Chung-II HYUN ,  Jung-Dal CHOI

IPC: H01L27/10

CPC classification number: H01L27/10 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66636

Abstract: A semiconductor memory device includes linear patterns disposed between isolation trenches extending in a first direction in a semiconductor device and having a first crystal direction the same as the semiconductor substrate. A bridge pattern connects at least two adjacent linear patterns and includes a semiconductor material having a second crystal direction different from the first crystal direction. A first isolation layer pattern is disposed in at least one of the isolation trenches in a field region of the semiconductor substrate. Memory cells are disposed on at least one of the linear patterns.

Abstract translation: 半导体存储器件包括设置在半导体器件中沿第一方向延伸并具有与半导体衬底相同的第一晶体方向的隔离沟槽之间的线状图案。 桥模式连接至少两个相邻的线状图案，并且包括具有与第一晶体方向不同的第二晶体方向的半导体材料。 第一隔离层图案设置在半导体衬底的场区域中的至少一个隔离沟槽中。 存储单元被布置在至少一个线性图案上。