公开(公告)号：US11049846B2

公开(公告)日：2021-06-29

申请号：US16548406

申请日：2019-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-hee Uh ,  Sung-min Kang ,  Jun-gu Kang ,  Seung-hee Go ,  Young-mok Kim

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/495 ,  H01L21/768 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  G09G3/20

Abstract: An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.

公开(公告)号：US11721640B2

公开(公告)日：2023-08-08

申请号：US17543920

申请日：2021-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-gu Kang ,  Young-mok Kim ,  Woon-bae Kim ,  Dae-cheol Seong ,  Yune-seok Chung

IPC: H01L23/552 ,  H01L23/48 ,  H01L23/00 ,  H01L21/74 ,  H01L27/12

CPC classification number: H01L23/552 ,  H01L21/743 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L27/1203 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/09103 ,  H01L2224/1403

Abstract: An integrated circuit chip includes an SOI substrate having a structure in which a bulk substrate, a buried insulating film, and a semiconductor body layer are sequentially stacked, a conductive ion implantation region formed at a position adjacent to the buried insulating film in the bulk substrate, an integrated circuit portion formed on an active surface of the semiconductor body layer, and a penetrating electrode portion arranged at a position spaced apart from the integrated circuit portion in a horizontal direction, the penetrating electrode portion penetrating the semiconductor body layer and the buried insulating layer in a vertical direction, and the penetrating electrode portion connected to the conductive ion implantation region. An integrated circuit package and a display device include the integrated circuit chip.

公开(公告)号：US11222853B2

公开(公告)日：2022-01-11

申请号：US16589589

申请日：2019-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-gu Kang ,  Young-mok Kim ,  Woon-bae Kim ,  Dae-cheol Seong ,  Yune-seok Chung

IPC: H01L23/552 ,  H01L23/48 ,  H01L23/00 ,  H01L21/74 ,  H01L27/12

Abstract: An integrated circuit chip includes an SOI substrate having a structure in which a bulk substrate, a buried insulating film, and a semiconductor body layer are sequentially stacked, a conductive ion implantation region formed at a position adjacent to the buried insulating film in the bulk substrate, an integrated circuit portion formed on an active surface of the semiconductor body layer, and a penetrating electrode portion arranged at a position spaced apart from the integrated circuit portion in a horizontal direction, the penetrating electrode portion penetrating the semiconductor body layer and the buried insulating layer in a vertical direction, and the penetrating electrode portion connected to the conductive ion implantation region. An integrated circuit package and a display device include the integrated circuit chip.

公开(公告)号：US11569206B2

公开(公告)日：2023-01-31

申请号：US17338630

申请日：2021-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-hee Uh ,  Sung-min Kang ,  Jun-gu Kang ,  Seung-hee Go ,  Young-mok Kim

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/495 ,  H01L21/768 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  G09G3/20

Abstract: An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.

公开(公告)号：US11121127B2

公开(公告)日：2021-09-14

申请号：US16589773

申请日：2019-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-gu Kang ,  Young-mok Kim ,  Woon-bae Kim ,  Dae-cheol Seong ,  Yune-seok Chung

IPC: H01L27/06 ,  H01L23/528 ,  H01L23/48

Abstract: An integrated circuit chip includes a circuit structure, a grounding structure, a bonding layer between the circuit structure and the grounding structure. The circuit structure includes a first substrate, an FEOL structure, and a BEOL structure. The grounding structure includes a second substrate and a grounding conductive layer. The integrated circuit chip includes a first penetrating electrode portion connected to the grounding conductive layer based on extending through the first substrate, the FEOL structure, the BEOL structure, and the bonding layer such that the first penetrating electrode portion is isolated from direct contact with the integrated circuit portion in a horizontal direction extending parallel to an active surface of the first substrate. An integrated circuit package and a display device each include the integrated circuit chip.