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公开(公告)号：US11963361B2
公开(公告)日：2024-04-16
申请号：US17140277
申请日：2021-01-04
发明人： Changsun Hwang , Youngjin Kwon , Gihwan Kim , Hansol Seok , Dongseog Eun , Jongheun Lim
CPC分类号： H10B43/40 , H01L23/5226 , H10B41/27 , H10B41/41 , H10B43/27
摘要： An integrated circuit device includes: a substrate having a cell region, a peripheral circuit region, and an interconnection region between the cell region and the peripheral circuit region; a first cell stack structure and a second cell stack structure on the first cell stack structure, each including a plurality of insulating layers and a plurality of word line structures alternately stacked on the substrate; and a dummy stack structure located at a same vertical level as the second cell stack structure, and including a plurality of dummy insulating layers and a plurality of dummy support layers alternately stacked in the peripheral circuit region.
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公开(公告)号：US11895827B2
公开(公告)日：2024-02-06
申请号：US17469469
申请日：2021-09-08
发明人： Giyong Chung , Youngjin Kwon , Dongseog Eun
IPC分类号： H10B12/00
CPC分类号： H10B12/395 , H10B12/0383 , H10B12/50
摘要： A vertical-type nonvolatile memory device has a multi-stack structure with reduced susceptibility to mis-alignment of a vertical channel layer. This nonvolatile memory device includes: (i) a main chip area including a cell area and an extension area arranged to have a stepped structure, with the cell area and the extension area formed in a multi-stack structure, and (ii) an outer chip area, which surrounds the main chip area and includes a step key therein. The main chip area includes a first layer on a substrate and a second layer on the first layer. A lower vertical channel layer is arranged in the first layer. The step key includes an alignment vertical channel layer, and a top surface of the alignment vertical channel layer is lower than a top surface of the lower vertical channel layer.
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公开(公告)号：US20220199626A1
公开(公告)日：2022-06-23
申请号：US17469469
申请日：2021-09-08
发明人： Giyong Chung , Youngjin Kwon , Dongseog Eun
IPC分类号： H01L27/108
摘要： A vertical-type nonvolatile memory device has a multi-stack structure with reduced susceptibility to mis-alignment of a vertical channel layer. This nonvolatile memory device includes: (i) a main chip area including a cell area and an extension area arranged to have a stepped structure, with the cell area and the extension area formed in a multi-stack structure, and (ii) an outer chip area, which surrounds the main chip area and includes a step key therein. The main chip area includes a first layer on a substrate and a second layer on the first layer. A lower vertical channel layer is arranged in the first layer. The step key includes an alignment vertical channel layer, and a top surface of the alignment vertical channel layer is lower than a top surface of the lower vertical channel layer.
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公开(公告)号：US20240224533A1
公开(公告)日：2024-07-04
申请号：US18605115
申请日：2024-03-14
发明人： Changsun Hwang , Youngjin Kwon , Gihwan Kim , Hansol Seok , Dongseog Eun , Jongheun Lim
IPC分类号： H10B43/40 , H01L23/522 , H10B41/27 , H10B41/41 , H10B43/27
CPC分类号： H10B43/40 , H01L23/5226 , H10B41/27 , H10B41/41 , H10B43/27
摘要： An integrated circuit device includes: a substrate having a cell region, a peripheral circuit region, and an interconnection region between the cell region and the peripheral circuit region; a first cell stack structure and a second cell stack structure on the first cell stack structure, each including a plurality of insulating layers and a plurality of word line structures alternately stacked on the substrate; and a dummy stack structure located at a same vertical level as the second cell stack structure, and including a plurality of dummy insulating layers and a plurality of dummy support layers alternately stacked in the peripheral circuit region.
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5.发明公开公开(公告)号：US20240138141A1
公开(公告)日：2024-04-25
申请号：US18402144
申请日：2024-01-02
发明人： Giyong Chung , Youngjin Kwon , Dongseog Eun
IPC分类号： H10B12/00
CPC分类号： H10B12/395 , H10B12/0383 , H10B12/50
摘要： A vertical-type nonvolatile memory device has a multi-stack structure with reduced susceptibility to mis-alignment of a vertical channel layer. This nonvolatile memory device includes: (i) a main chip area including a cell area and an extension area arranged to have a stepped structure, with the cell area and the extension area formed in a multi-stack structure, and (ii) an outer chip area, which surrounds the main chip area and includes a step key therein. The main chip area includes a first layer on a substrate and a second layer on the first layer. A lower vertical channel layer is arranged in the first layer. The step key includes an alignment vertical channel layer, and a top surface of the alignment vertical channel layer is lower than a top surface of the lower vertical channel layer.
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公开(公告)号：US11563023B2
公开(公告)日：2023-01-24
申请号：US16792256
申请日：2020-02-16
发明人： Jongseon Ahn , Youngjin Kwon , Jeehoon Han
IPC分类号： H01L27/11582 , H01L27/1157 , H01L27/11565 , H01L29/423
摘要： A semiconductor device includes a channel structure arranged on a substrate and extending in a first direction perpendicular to a top surface of the substrate, the channel structure including a channel layer and a gate insulating layer; a plurality of insulating layers arranged on the substrate and surrounding the channel structure, the plurality of insulating layers spaced apart from each other in the first direction; a plurality of first gate electrodes surrounding the channel structure; and a plurality of second gate electrodes surrounding the channel structure. Between adjacent insulating layers from among the plurality of insulating layers are arranged a first gate electrode from among the plurality of first gate electrodes spaced apart along the first direction from a second gate electrode from among the plurality of second gate electrodes.
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