公开(公告)号：US10008505B2

公开(公告)日：2018-06-26

申请号：US15198035

申请日：2016-06-30

申请人： Samsung Electronics Co., Ltd.

发明人： Jun-Noh Lee ,  Youngkuk Kim ,  Sangyeol Kang ,  Joonsoo Park ,  KiVin Im

IPC分类号： H01L27/108

CPC分类号： H01L27/10855 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10888

摘要： A method for manufacturing a semiconductor device may include forming contact pads spaced apart from each other in a first direction on a substrate and between first insulating patterns; forming first holes between the first insulating patterns and having bottom ends adjacent top surfaces of the contact pads; forming second holes between second insulating patterns and overlapping with partial portions of the first holes in a second direction perpendicular to the first direction; and forming a bottom electrode layer including first portions to cover the bottom ends of the first holes and sidewalls of the second holes. In forming the first and second holes, the first and second holes are formed simultaneously.

公开(公告)号：US09305928B2

公开(公告)日：2016-04-05

申请号：US14175076

申请日：2014-02-07

申请人： Samsung Electronics Co., Ltd.

发明人： Youngkuk Kim ,  Ho-Kyun An ,  Jaehyun Yeo ,  Badro Im ,  HanJin Lim ,  Sungho Jang ,  Insang Jeon

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/8234

CPC分类号： H01L27/10894 ,  H01L21/823412 ,  H01L21/823462 ,  H01L27/10814 ,  H01L27/10861

摘要： Semiconductor devices having a silicon-germanium channel layer and methods of forming the semiconductor devices are provided. The methods may include forming a silicon-germanium channel layer on a substrate in a peripheral circuit region and sequentially forming a first insulating layer and a second insulating layer on the silicon-germanium channel layer. The methods may also include forming a conductive layer on the substrate, which includes a cell array region and the peripheral circuit region, and patterning the conductive layer to form a conductive line in the cell array region and a gate electrode in the peripheral circuit region. The first insulating layer may be formed at a first temperature and the second insulating layer may be formed at a second temperature higher than the first temperature.

摘要翻译： 提供具有硅 - 锗沟道层的半导体器件和形成半导体器件的方法。 所述方法可以包括在外围电路区域中的衬底上形成硅 - 锗沟道层，并且在硅 - 锗沟道层上依次形成第一绝缘层和第二绝缘层。 该方法还可以包括在衬底上形成导电层，该导电层包括电池阵列区域和外围电路区域，以及图案化导电层以在电池阵列区域中形成导线以及在外围电路区域中形成栅极电极。 第一绝缘层可以在第一温度下形成，并且第二绝缘层可以在高于第一温度的第二温度下形成。