公开(公告)号：US09666433B2

公开(公告)日：2017-05-30

申请号：US15130515

申请日：2016-04-15

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Badro Im ,  Yoonchul Cho ,  Sangyeol Kang ,  Daehyun Kim ,  Dongkak Lee ,  Jun-Noh Lee ,  Bonghyun Kim ,  Kongsoo Lee

IPC分类号： H01L21/311 ,  H01L21/033 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/3205

CPC分类号： H01L21/0337 ,  H01L21/02112 ,  H01L21/02129 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32055 ,  H01L21/32139

摘要： Carbon-containing patterns are formed on an etch target layer, side surfaces of the carbon-containing patterns are treated by a hydrophilic process, poly-crystalline silicon spacers are formed on the side surfaces of the carbon-containing patterns after the hydrophilic process has been performed, and the etch target layer is patterned using the poly-crystalline silicon spacers as an etch mask.

公开(公告)号：US10553449B2

公开(公告)日：2020-02-04

申请号：US15700491

申请日：2017-09-11

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sun-Hye Hwang ,  Youn-Joung Cho ,  Won-Woong Chung ,  Nam-Gun Kim ,  Kong-Soo Lee ,  Badro Im ,  Yoon-Chul Cho

IPC分类号： H01L21/3213 ,  H01L21/311

摘要： A method of forming a pattern includes forming an etch target layer on a substrate, forming sacrificial patterns on the etch target layer, the sacrificial patterns including a carbon-containing material, providing a silicon-sulfur compound or a sulfur-containing gas onto the sacrificial patterns to form a seed layer, providing a silicon precursor onto the seed layer to form silicon-containing mask patterns, and at least partially etching the etch target layer using the mask patterns.

公开(公告)号：US10224213B2

公开(公告)日：2019-03-05

申请号：US15444381

申请日：2017-02-28

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Kyungmun Byun ,  Sinhae Do ,  Badro Im

IPC分类号： H01L21/308 ,  H01L21/28 ,  H01L21/3213

摘要： A method for forming patterns of a semiconductor device includes sequentially forming a hard mask layer, a sacrificial layer, and an anti-reflection layer on a substrate, the substrate including a cell region and a peripheral circuit region, patterning the sacrificial layer to form a first sacrificial pattern on the cell region and a second sacrificial pattern on the peripheral circuit region, forming spacers covering sidewalls of the first and second sacrificial patterns, and removing the first sacrificial pattern. The anti-reflection layer includes a lower anti-reflection layer and an upper anti-reflection layer which are formed of materials different from each other. In the patterning of the sacrificial layer, the anti-reflection layer is patterned to form a first anti-reflection pattern on the first sacrificial pattern and a second anti-reflection pattern on the second sacrificial pattern. The second anti-reflection pattern remains when the first sacrificial pattern is removed.

公开(公告)号：US10141200B2

公开(公告)日：2018-11-27

申请号：US15613822

申请日：2017-06-05

申请人： Samsung Electronics Co., Ltd.

发明人： Kyung-Mun Byun ,  Badro Im ,  Hong-Rae Kim ,  Sin-Hae Do ,  Gyeong-Deok Park

IPC分类号： H01L21/336 ,  H01L21/48 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/67 ,  H01L21/764 ,  H01L21/8234

摘要： In a method of manufacturing a semiconductor memory device, a plurality of first conductive structures including a first conductive pattern and a hard mask are sequentially stacked on a substrate. A plurality of preliminary spacer structures including first spacers, sacrificial spacers and second spacers are sequentially stacked on sidewalls of the conductive structures. A plurality of pad structures are formed on the substrate between the preliminary spacer structures, and define openings exposing an upper portion of the sacrificial spacers. A first mask pattern is formed to cover surfaces of the pad structures, and expose the upper portion of the sacrificial spacers. The sacrificial spacers are removed to form first spacer structures having respective air spacers, and the first spacer structures include the first spacers, the air spacers and the second spacers sequentially stacked on the sidewalls of the conductive structures.

公开(公告)号：US09305928B2

公开(公告)日：2016-04-05

申请号：US14175076

申请日：2014-02-07

申请人： Samsung Electronics Co., Ltd.

发明人： Youngkuk Kim ,  Ho-Kyun An ,  Jaehyun Yeo ,  Badro Im ,  HanJin Lim ,  Sungho Jang ,  Insang Jeon

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/8234

CPC分类号： H01L27/10894 ,  H01L21/823412 ,  H01L21/823462 ,  H01L27/10814 ,  H01L27/10861

摘要： Semiconductor devices having a silicon-germanium channel layer and methods of forming the semiconductor devices are provided. The methods may include forming a silicon-germanium channel layer on a substrate in a peripheral circuit region and sequentially forming a first insulating layer and a second insulating layer on the silicon-germanium channel layer. The methods may also include forming a conductive layer on the substrate, which includes a cell array region and the peripheral circuit region, and patterning the conductive layer to form a conductive line in the cell array region and a gate electrode in the peripheral circuit region. The first insulating layer may be formed at a first temperature and the second insulating layer may be formed at a second temperature higher than the first temperature.

摘要翻译： 提供具有硅 - 锗沟道层的半导体器件和形成半导体器件的方法。 所述方法可以包括在外围电路区域中的衬底上形成硅 - 锗沟道层，并且在硅 - 锗沟道层上依次形成第一绝缘层和第二绝缘层。 该方法还可以包括在衬底上形成导电层，该导电层包括电池阵列区域和外围电路区域，以及图案化导电层以在电池阵列区域中形成导线以及在外围电路区域中形成栅极电极。 第一绝缘层可以在第一温度下形成，并且第二绝缘层可以在高于第一温度的第二温度下形成。