公开(公告)号：US10748909B2

公开(公告)日：2020-08-18

申请号：US16711833

申请日：2019-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwon Ma ,  Jun-Noh Lee ,  Dong-Hyun Im ,  Youngseok Kim ,  Kongsoo Lee

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532

Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.

公开(公告)号：US10008505B2

公开(公告)日：2018-06-26

申请号：US15198035

申请日：2016-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Noh Lee ,  Youngkuk Kim ,  Sangyeol Kang ,  Joonsoo Park ,  KiVin Im

IPC: H01L27/108

CPC classification number: H01L27/10855 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10888

Abstract: A method for manufacturing a semiconductor device may include forming contact pads spaced apart from each other in a first direction on a substrate and between first insulating patterns; forming first holes between the first insulating patterns and having bottom ends adjacent top surfaces of the contact pads; forming second holes between second insulating patterns and overlapping with partial portions of the first holes in a second direction perpendicular to the first direction; and forming a bottom electrode layer including first portions to cover the bottom ends of the first holes and sidewalls of the second holes. In forming the first and second holes, the first and second holes are formed simultaneously.

公开(公告)号：US10535663B2

公开(公告)日：2020-01-14

申请号：US16245307

申请日：2019-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwon Ma ,  Jun-Noh Lee ,  Dong-Hyun Im ,  Youngseok Kim ,  Kongsoo Lee

IPC: H01L27/108 ,  H01L21/768

Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.

公开(公告)号：US20140367774A1

公开(公告)日：2014-12-18

申请号：US14294412

申请日：2014-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Ryeol Yoo ,  Jun-Noh Lee ,  Dong-Chan Kim ,  Han-Jin Lim

IPC: H01L29/423 ,  H01L29/49

CPC classification number: H01L29/4236 ,  H01L27/10876 ,  H01L29/4966 ,  H01L29/4983

Abstract: Semiconductor devices are provided including a first trench in a semiconductor substrate; a first insulating film in the first trench; a first conductive film on the first insulating film, the first conductive film having upper and lower portions and filling at least a portion of the first trench; and a first work function adjustment film having first and second portions, a first lower work function adjustment film portion and a first upper work function adjustment portion. The first lower work function adjustment film portion overlaps the lower portion of the first conductive film and the first upper work function adjustment film portion overlaps the upper portion of the first conductive film between the first insulating film and the first conductive film.

Abstract translation: 提供半导体器件，其包括半导体衬底中的第一沟槽; 第一沟槽中的第一绝缘膜; 在所述第一绝缘膜上的第一导电膜，所述第一导电膜具有上部和下部并填充所述第一沟槽的至少一部分; 以及具有第一和第二部分的第一功能调整膜，第一下部功能调整膜部分和第一上部功能调整部分。 第一下功函数调整膜部与第一导电膜的下部重叠，第一上功函调整膜部与第一绝缘膜与第一导电膜之间的第一导电膜的上部重叠。

公开(公告)号：US10211210B2

公开(公告)日：2019-02-19

申请号：US15603668

申请日：2017-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwon Ma ,  Jun-Noh Lee ,  Dong-Hyun Im ,  Youngseok Kim ,  Kongsoo Lee

IPC: H01L27/108 ,  H01L21/768

Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.

公开(公告)号：US20200119021A1

公开(公告)日：2020-04-16

申请号：US16711833

申请日：2019-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwon MA ,  Jun-Noh Lee ,  Dong-Hyun IM ,  Youngseok Kim ,  Kongsoo Lee

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/485

Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.

公开(公告)号：US20170345824A1

公开(公告)日：2017-11-30

申请号：US15603668

申请日：2017-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwon MA ,  Jun-Noh Lee ,  Dong-Hyun Im ,  Youngseok Kim ,  Kongsoo Lee

IPC: H01L27/108 ,  H01L21/768

CPC classification number: H01L27/10888 ,  H01L21/76805 ,  H01L21/76883 ,  H01L21/76895 ,  H01L27/10811 ,  H01L27/10855 ,  H01L27/10885

Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.

公开(公告)号：US09666433B2

公开(公告)日：2017-05-30

申请号：US15130515

申请日：2016-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Badro Im ,  Yoonchul Cho ,  Sangyeol Kang ,  Daehyun Kim ,  Dongkak Lee ,  Jun-Noh Lee ,  Bonghyun Kim ,  Kongsoo Lee

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/3205

CPC classification number: H01L21/0337 ,  H01L21/02112 ,  H01L21/02129 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32055 ,  H01L21/32139

Abstract: Carbon-containing patterns are formed on an etch target layer, side surfaces of the carbon-containing patterns are treated by a hydrophilic process, poly-crystalline silicon spacers are formed on the side surfaces of the carbon-containing patterns after the hydrophilic process has been performed, and the etch target layer is patterned using the poly-crystalline silicon spacers as an etch mask.