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    Low power clock gating cell and an integrated circuit including the same
    1.
    发明授权
    Low power clock gating cell and an integrated circuit including the same 有权

    公开(公告)号：US11658656B2

    公开(公告)日：2023-05-23

    申请号：US17515607

    申请日：2021-11-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunchul Hwang ,  Youngo Lee

    IPC: H03K17/687 ,  H03K3/356

    CPC classification number: H03K17/6871 ,  H03K3/356

    Abstract: A clock gating cell including: a first circuit configured to receive an enable signal and an inverted output clock signal and generate a first signal through a first node; a second circuit configured to receive the first signal and generate an inverted first signal; a third circuit configured to receive the first signal, the inverted first signal, and an input clock signal, generate the first signal by being connected to the first circuit through the first node, and generate the inverted output clock signal through a second node; and a fourth circuit configured to receive the first signal, generate the inverted output clock signal by being connected to the third circuit through the second node, and generate the output clock signal, wherein the third circuit includes a pair of transistors receiving the input clock signal.

    Clock gating cell with low power and integrated circuit including the same
    3.
    发明授权
    Clock gating cell with low power and integrated circuit including the same 有权

    公开(公告)号：US11190186B2

    公开(公告)日：2021-11-30

    申请号：US17222197

    申请日：2021-04-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngo Lee ,  Ahreum Kim

    IPC: H03K19/00 ,  H03K3/012

    Abstract: In an integrated circuit including a clock gating cell based on a set-reset (SR) latch, the clock gating cell includes a first 2-input logic gate configured to receive a clock input and a first signal, and generate a second signal, a first inverter configured to receive the second signal, and generate a clock output, and a 4-input logic gate including a 4-input keeping logic gate configured to generate the SR latch by being cross-coupled to the first 2-input logic gate and keep a level of the first signal.

    Integrated clock gating circuit
    4.
    发明授权
    Integrated clock gating circuit 有权

    公开(公告)号：US11063592B2

    公开(公告)日：2021-07-13

    申请号：US16991659

    申请日：2020-08-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Youngo Lee ,  Ahreum Kim ,  Minsu Kim

    IPC: H03K19/00 ,  H03K3/037 ,  H03K3/33 ,  G06F1/08 ,  H03K17/687

    Abstract: An integrated circuit gating circuit includes a first control stage that outputs a first internal signal based on an enable signal and a clock signal, a second control stage that outputs a second internal signal based on the first internal signal and the clock signal, and an output driver that outputs an output clock signal based on the second internal signal. The second control stage includes a first multi-finger transistor that is connected between a second node outputting the second internal signal and the 0-th node and operates based on the clock signal. A first portion of the first multi-finger transistor is formed in a first row defined on a semiconductor substrate, and a second portion of the first multi-finger transistor is formed in a second row defined on the semiconductor substrate.

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