公开(公告)号：US20180158911A1

公开(公告)日：2018-06-07

申请号：US15887773

申请日：2018-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yuichiro SASAKI ,  Bong Soo KIM ,  Tae Gon KIM ,  Yoshiya MORIYAMA ,  Seung Hyun SONG ,  Alexander SCHMIDT ,  Abraham YOO ,  Heung Soon LEE ,  Kyung In CHOI

IPC: H01L29/10 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L21/2236 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.

公开(公告)号：US20220028895A1

公开(公告)日：2022-01-27

申请号：US17494275

申请日：2021-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Weonhong KIM ,  Pilkyu KANG ,  Yuichiro SASAKI ,  Sungkeun LIM ,  Yongho HA ,  Sangjin HYUN ,  Kughwan KIM ,  Seungha OH

IPC: H01L27/12 ,  H01L21/762 ,  H01L27/02

Abstract: An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.

公开(公告)号：US20210335707A1

公开(公告)日：2021-10-28

申请号：US17367773

申请日：2021-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yuichiro SASAKI ,  Sungkeun LIM ,  Pil-Kyu KANG ,  Weonhong KIM ,  Seungha OH ,  Yongho HA ,  Sangjin HYUN

IPC: H01L23/522 ,  H01L23/50 ,  H01L23/528

Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, an active pattern on the first surface, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, and a power delivery network on the second surface, the power delivery network electrically connected to the power rail. The semiconductor layer includes an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.

公开(公告)号：US20200373331A1

公开(公告)日：2020-11-26

申请号：US16807410

申请日：2020-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Weonhong KIM ,  Pilkyu KANG ,  Yuichiro SASAKI ,  Sungkeun LIM ,  Yongho HA ,  Sangjin HYUN ,  Kughwan KIM ,  Seungha OH

IPC: H01L27/12 ,  H01L27/02 ,  H01L21/762

Abstract: An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.

公开(公告)号：US20170373151A1

公开(公告)日：2017-12-28

申请号：US15424081

申请日：2017-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yuichiro SASAKI ,  Bong Soo KIM ,  Tae Gon KIM ,  Yoshiya MORIYAMA ,  Seung Hyun SONG ,  Alexander SCHMIDT ,  Abraham YOO ,  Heung Soon LEE ,  Kyung In CHOI

IPC: H01L29/10 ,  H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L21/2236 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.