公开(公告)号：US20230354605A1

公开(公告)日：2023-11-02

申请号：US18175198

申请日：2023-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Teawon KIM ,  Yurim KIM ,  Seunghee LEE ,  Seungwoo JANG ,  Yong-Suk TAK

IPC: H10B43/27 ,  H10B43/10 ,  H10B43/40 ,  H10B41/40 ,  H10B41/10 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B43/10 ,  H10B43/40 ,  H10B41/40 ,  H10B41/10 ,  H10B41/27

Abstract: A semiconductor memory device includes a bit line, a channel pattern including a horizontal channel portion on the bit line and a vertical channel portion vertically protruding from the horizontal channel portion, a word line on the horizontal channel portion and on a sidewall of the vertical channel portion, and a gate insulating pattern between the word line and the channel pattern. The channel pattern includes an oxide semiconductor and includes first, second, and third channel layers sequentially stacked. The first to third channel layers include a first metal, and the second channel layer further includes a second metal different from the first metal. At least a portion of the first channel layer contacts the bit line.

公开(公告)号：US20230052762A1

公开(公告)日：2023-02-16

申请号：US17697423

申请日：2022-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Teawon KIM ,  Hyung Joon KIM ,  Yong-Suk TAK ,  Yurim KIM ,  Kongsoo LEE

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/423

Abstract: Disclosed is a semiconductor device comprising an oxide semiconductor layer on a substrate and including a first part and a pair of second parts that are spaced apart from each other across the first part, a gate electrode on the first part of the oxide semiconductor layer, and a pair of electrodes on corresponding second parts of the oxide semiconductor layer. A first thickness of the first part of the oxide semiconductor layer is less than a second thickness of each second part of the oxide semiconductor layer. A number of oxygen vacancies in the first part of the oxide semiconductor layer is less than a number of oxygen vacancies in each second part of the oxide semiconductor layer.

公开(公告)号：US20240251545A1

公开(公告)日：2024-07-25

申请号：US18493924

申请日：2023-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Seong PARK ,  Seung Hee LEE ,  Yong-Suk TAK ,  Dong-Gyu KIM ,  Yu Rim KIM ,  Tae Won KIM ,  Dong-Hyeon LEE

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/05

Abstract: There is provided a semiconductor memory device having improved integration and electrical characteristics. The semiconductor memory device includes a bit line extending in a first direction on a substrate, a first channel pattern disposed on the bit line, a second channel pattern disposed on the bit line and spaced apart from the first channel pattern in the first direction, a first word line disposed between the first channel pattern and the second channel pattern extends in a second direction, a second word line disposed between the first channel pattern and the second channel pattern, extends in the second direction, and is spaced apart from the first word line in the first direction, and a first capacitor and a second capacitor disposed on and connected to the first channel pattern and the second channel pattern, respectively, wherein each of the first channel pattern and the second channel pattern includes a first metal oxide pattern including indium (In), gallium (Ga) and tin (Sn), and a position of a peak of tin is different from a position of a peak of gallium in a spatial composition distribution of the first metal oxide pattern.

公开(公告)号：US20140145306A1

公开(公告)日：2014-05-29

申请号：US14170758

申请日：2014-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wan-Don KIM ,  Beom-Seok KIM ,  Yong-Suk TAK ,  Kyu-Ho CHO ,  Seung-hwan LEE ,  Oh-Seong KWON ,  Geun-Kyu CHOI

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L24/32 ,  H01L28/90 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/8385

Abstract: A plurality of metal patterns are disposed on a substrate. A support structure is provided between the plurality of metal patterns. The support structure has a supporter and a glue layer. Each of the plurality of metal patterns has a greater vertical length than a horizontal length on the substrate when viewed from a cross-sectional view. The supporter has a band gap energy of at least 4.5 eV. The glue layer is in contact with the plurality of metal patterns. The supporter and the glue layer are formed of different materials.

Abstract translation: 多个金属图案设置在基板上。 在多个金属图案之间提供支撑结构。 支撑结构具有支撑体和胶层。 当从横截面视图观察时，多个金属图案中的每一个具有比基板上的水平长度更大的垂直长度。 该支架具有至少4.5eV的带隙能量。 胶层与多个金属图案接触。 支撑体和胶层由不同的材料形成。

公开(公告)号：US20130217203A1

公开(公告)日：2013-08-22

申请号：US13845765

申请日：2013-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Oh-Seong KWON ,  Kyu-Ho CHO ,  Wan-Don KIM ,  Beom-Seok KIM ,  Yong-Suk TAK

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L27/10852 ,  H01L27/10876 ,  H01L28/65

Abstract: A capacitor in a semiconductor memory device comprises a lower electrode on a substrate that is formed of a conductive metal oxide having a rutile crystalline structure, a titanium oxide dielectric layer on the lower electrode that has a rutile crystalline structure and includes impurities for reducing a leakage current, and an upper electrode on the titanium oxide dielectric layer. A method of forming a capacitor in a semiconductor device comprise steps of forming a lower electrode on a substrate that includes a conductive metal oxide having a rutile crystalline structure, forming a titanium oxide dielectric layer on the lower electrode that has a rutile crystalline structure and impurities for reducing a leakage current, and forming an upper electrode on the titanium oxide dielectric layer.

Abstract translation: 半导体存储器件中的电容器包括由具有金红石晶体结构的导电金属氧化物形成的衬底上的下电极，下电极上的具有金红石晶体结构的氧化钛电介质层，并且包括用于减少漏电的杂质 电流和氧化钛电介质层上的上电极。 在半导体器件中形成电容器的方法包括以下步骤：在包括具有金红石晶体结构的导电金属氧化物的衬底上形成下电极，在具有金红石晶体结构的下电极上形成氧化钛电介质层和杂质 用于减少漏电流，以及在氧化钛电介质层上形成上电极。

公开(公告)号：US20180083007A1

公开(公告)日：2018-03-22

申请号：US15613334

申请日：2017-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juri LEE ,  Yong-Suk TAK ,  Sung-Dae SUK ,  Seungmin SONG

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/1037 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/78696

Abstract: Disclosed are semiconductor devices including a field effect transistor and methods of manufacturing the same. The semiconductor device comprises a device isolation layer in an upper portion of a substrate, first active patterns on a first region of the substrate and second active patterns on a second region of the substrate, gate structures extending in one direction and running across the first and second active patterns, and a blocking layer on a recessed region of the device isolation layer of the first region. Each of the first and second active patterns comprises a plurality of semiconductor patterns that are vertically stacked and spaced apart from each other. The semiconductor patterns of the first active patterns have conductivity different from that of the semiconductor patterns of the second active patterns. The blocking layer is limited on the first region.

公开(公告)号：US20170317213A1

公开(公告)日：2017-11-02

申请号：US15410238

申请日：2017-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mi-Seon PARK ,  Gi-Gwan PARK ,  Tae-Jong LEE ,  Yong-Suk TAK ,  Ki-Yeon PARK

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L29/7851 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/0228 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure directly on a sidewall of the gate structure, and a source/drain layer on a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a silicon oxycarbonitride (SiOCN) pattern and a silicon dioxide (SiO2) pattern sequentially stacked.

公开(公告)号：US20170148901A1

公开(公告)日：2017-05-25

申请号：US15422907

申请日：2017-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYUNGIN CHOI ,  Sunghyun CHOI ,  Yong-Suk TAK ,  BONYOUNG KOO ,  JAEJONG HAN

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/223

CPC classification number: H01L29/66803 ,  H01L21/2236 ,  H01L21/762 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method of manufacturing a semiconductor device includes forming a preliminary fin-type active pattern extending in a first direction, forming a device isolation pattern covering a lower portion of the preliminary fin-type active pattern, forming a gate structure extending in a second direction and crossing over the preliminary fin-type active pattern, forming a fin-type active pattern having a first region and a second region, forming a preliminary impurity-doped pattern on the second region by using a selective epitaxial-growth process, and forming an impurity-doped pattern by injecting impurities using a plasma doping process, wherein the upper surface of the first region is at a first level and the upper surface of the second region is at a second level lower than the first level.

公开(公告)号：US20160372567A1

公开(公告)日：2016-12-22

申请号：US15134906

申请日：2016-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Suk TAK ,  Gyeom KIM ,  Ki-Yeon PARK ,  Sung-Hyun CHOI ,  Bon-Young KOO

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/165 ,  H01L29/08 ,  H01L29/78 ,  H01L29/161

CPC classification number: H01L29/6656 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate including an active fin structure, a plurality of gate structures, a first spacer on sidewalls of each of the gate structures, and a second spacer on sidewalls of the first spacer. The active fin structure may extend in a first direction and including a plurality of active fins with adjacent active fins divided by a recess. Each of the plurality of gate structures may extend in a second direction crossing the first direction, and may cover the active fins. The first spacer may include silicon oxycarbonitride (SiOCN), and may have a first carbon concentration. The second spacer may include SiOCN and may have a second carbon concentration which is different from the first carbon concentration. The semiconductor device may have a low parasitic capacitance and good electrical characteristics.

Abstract translation: 半导体器件包括：衬底，其包括有源鳍结构，多个栅极结构，每个栅极结构的侧壁上的第一间隔物，以及在第一间隔物的侧壁上的第二间隔物。 主动翅片结构可以在第一方向上延伸并且包括多个活动翅片，相邻的活动翅片由凹部分开。 多个栅极结构中的每一个可以在与第一方向交叉的第二方向上延伸，并且可以覆盖活动鳍片。 第一间隔物可以包括硅碳氮氧化物（SiOCN），并且可以具有第一碳浓度。 第二间隔物可以包括SiOCN，并且可以具有不同于第一碳浓度的第二碳浓度。 半导体器件可以具有低寄生电容和良好的电特性。

公开(公告)号：US20250107065A1

公开(公告)日：2025-03-27

申请号：US18619490

申请日：2024-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Seong PARK ,  Jihyun KHO ,  Seunghee LEE ,  Yurim KIM ,  Yong-Suk TAK ,  Dong-Gyu KIM

IPC: H10B12/00

Abstract: A semiconductor device includes a semiconductor pattern, a dielectric layer on the semiconductor pattern, and a conductive pattern on the dielectric layer. Each of the semiconductor pattern and the dielectric layer includes impurities. The dielectric layer includes a concentration profile of impurities including a first variation section including a first concentration of impurities decreasing throughout the dielectric layer toward the semiconductor pattern, and a second variation section including a second concentration of impurities decreasing throughout the dielectric layer toward the semiconductor pattern.