公开(公告)号：US20240096879A1

公开(公告)日：2024-03-21

申请号：US18298678

申请日：2023-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu Man HWANG ,  Sung Il PARK ,  Jin Chan YUN ,  Dong Kyu LEE

IPC: H01L27/088 ,  H01L21/822 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/088 ,  H01L21/8221 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/82345 ,  H01L21/823481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A semiconductor device is provided. The semiconductor device includes an active pattern extending in a first horizontal direction, a plurality of lower nanosheets stacked on the active pattern and spaced apart from one another in a vertical direction, a separation layer on the plurality of lower nanosheets, a plurality of upper nanosheets stacked on the separation layer and spaced apart from one another in the vertical direction, a gate electrode extending on the active pattern in a second horizontal direction, the gate electrode surrounding each of the plurality of lower nanosheets, the separation layer and the plurality of upper nano sheets, and a first conductive layer between the gate electrode and each of a top surface and a bottom surface of the plurality of upper nanosheets. The first conductive layer is not between the gate electrode and sidewalls of the plurality of upper nanosheets.

公开(公告)号：US20230326971A1

公开(公告)日：2023-10-12

申请号：US18149398

申请日：2023-01-03

Applicant: Samsung Electronics Co.,Ltd.

Inventor： Kyu Man HWANG ,  Sung ll Park ,  Jae Hyun Park ,  Do Young Choi

IPC: H01L29/10 ,  H01L29/78

CPC classification number: H01L29/1033 ,  H01L29/7851

Abstract: A semiconductor device including a lower pattern extending in a first direction, a gate electrode on the lower pattern and extending in a second direction, a lower channel pattern on the lower pattern and comprising at least one lower sheet pattern, an upper channel pattern on the lower channel pattern and comprising at least one upper sheet pattern, wherein the upper channel pattern is spaced apart from the lower channel pattern in a third direction, the gate electrode comprises a lower gate electrode through which the lower sheet pattern passes and an upper gate electrode through which the upper sheet pattern passes, the lower gate electrode comprises a lower conductive liner layer defining a trench and a lower filling layer filling the trench, and an entire bottom surface of the upper gate electrode is higher than an upper surface of the lower gate electrode, may be provided.