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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250151388A1

    公开(公告)日：2025-05-08

    申请号：US18738621

    申请日：2024-06-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dahye Kim ,  Jae Hyun Park ,  Jinchan Yun ,  Daihong Huh

    IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

    Abstract: A semiconductor device incudes: a plurality of lower channel patterns apart from each other; a plurality of upper channel patterns spaced apart from each other on the plurality of lower channel patterns; a gate structure surrounding the plurality of lower channel patterns and the plurality of upper channel patterns; a lower source/drain trench positioned on at least one side of the plurality of lower channel patterns; an upper source/drain trench positioned on at least one side of the plurality of upper channel patterns; a lower source/drain pattern positioned within the lower source/drain trench; and an upper source/drain pattern including first upper source/drain layers positioned on opposite sidewalls of the upper source/drain trench, and a second upper source/drain layer positioned between the first upper source/drain layers, in which the first upper source/drain layer does not cover at least a portion of the bottom surface of the upper source/drain trench.

    Analog front-end receiver and electronic device including the same
    2.
    发明授权
    Analog front-end receiver and electronic device including the same 有权

    公开(公告)号：US11901967B2

    公开(公告)日：2024-02-13

    申请号：US17380779

    申请日：2021-07-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byeong Gyu Park ,  Jae Hyun Park ,  Jun Han Bae ,  Ho-Bin Song

    IPC: H04B3/14

    CPC classification number: H04B3/14

    Abstract: Provided is an analog front-end receiver including: a first equalizer including a first block switch configured to receive a first differential signal through a first node, and configured to block the first differential signal in a first operation mode; a second equalizer including a second block switch configured to receive a second differential signal through a second node, and configured to block the second differential signal in the first operation mode; a terminating resistor provided between the first node and the second node, and configured to receive the first differential signal via the first node, and receive the second differential signal via the second node; and a low pass filter configured to receive a third differential signal converted by the terminating resistor from the first differential signal, and configured to receive a fourth differential signal converted by the terminating resistor from the second differential signal.

    SEMICONDUCTOR DEVICE
    3.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230326971A1

    公开(公告)日：2023-10-12

    申请号：US18149398

    申请日：2023-01-03

    Applicant: Samsung Electronics Co.,Ltd.

    Inventor： Kyu Man HWANG ,  Sung ll Park ,  Jae Hyun Park ,  Do Young Choi

    IPC: H01L29/10 ,  H01L29/78

    CPC classification number: H01L29/1033 ,  H01L29/7851

    Abstract: A semiconductor device including a lower pattern extending in a first direction, a gate electrode on the lower pattern and extending in a second direction, a lower channel pattern on the lower pattern and comprising at least one lower sheet pattern, an upper channel pattern on the lower channel pattern and comprising at least one upper sheet pattern, wherein the upper channel pattern is spaced apart from the lower channel pattern in a third direction, the gate electrode comprises a lower gate electrode through which the lower sheet pattern passes and an upper gate electrode through which the upper sheet pattern passes, the lower gate electrode comprises a lower conductive liner layer defining a trench and a lower filling layer filling the trench, and an entire bottom surface of the upper gate electrode is higher than an upper surface of the lower gate electrode, may be provided.

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230046546A1

    公开(公告)日：2023-02-16

    申请号：US17699724

    申请日：2022-03-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sungil Park ,  Jae Hyun Park ,  Doyoung Choi ,  Youngmoon Choi ,  Daewon Ha

    IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

    Abstract: A semiconductor device includes: an active pattern extending in a first direction on a substrate; a first lower source/drain pattern and a second lower source/drain pattern provided on the active pattern and spaced apart from each other in the first direction; a first upper source/drain pattern provided on the first lower source/drain pattern; a second upper source/drain pattern provided on the second lower source/drain pattern; and a gate electrode crossing the active pattern and extending in a second direction intersecting the first direction. The gate electrode includes an overlapping portion overlapping the active pattern in a third direction perpendicular to the first direction and the second direction. A length of the overlapping portion in the second direction is less than a length of the first lower source/drain pattern in the second direction.

    SEMICONDUCTOR DEVICE
    10.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230326994A1

    公开(公告)日：2023-10-12

    申请号：US18189621

    申请日：2023-03-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungil Park ,  Jae Hyun Park

    IPC: H01L29/66 ,  H01L27/082 ,  H01L29/08 ,  H01L29/10 ,  H01L27/102

    CPC classification number: H01L29/66303 ,  H01L27/082 ,  H01L27/1022 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/0804

    Abstract: A semiconductor device includes a semiconductor body having first and second surfaces opposite to each other. The semiconductor body includes a first well region having a first conductivity type, second and third well regions spaced apart from each other in a first direction with the first well region interposed therebetween and having a second conductivity type, first doped regions spaced apart from each other in a second direction intersecting the first direction in the first well region, a second doped region, which is adjacent to the second well region and has the second conductivity type, and a third doped region, which is adjacent to the third well region and has the second conductivity type. The second surface of the semiconductor body includes bottom surfaces of the first to third well regions, the plurality of first doped regions, the second doped region, and the third doped region.

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