公开(公告)号：US20190198323A1

公开(公告)日：2019-06-27

申请号：US16027692

申请日：2018-07-05

Applicant: Samsung Electronics Co. Ltd.

Inventor： Jung Han Lee ,  Byoung-gi Kim ,  Jong Pil Kim ,  Kihwan Lee

IPC: H01L21/225 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/762 ,  H01L23/532

Abstract: A method for manufacturing a semiconductor device includes performing a first ion implantation process on a substrate to form a lower dopant region in the substrate, patterning the substrate having the lower dopant region to form active patterns, and performing a second ion implantation process on the active patterns to form an upper dopant region in an upper portion of each of the active patterns. The lower and upper dopant regions have a same conductivity type.

公开(公告)号：US20190206867A1

公开(公告)日：2019-07-04

申请号：US16030224

申请日：2018-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Han LEE ,  Sungchul Park ,  Yunil Lee ,  Byoung-gi Kim ,  Yeongmin Jeon ,  Daewon Ha ,  Inchan Hwang ,  Jae Hyun Park ,  Woocheol Shin

IPC: H01L27/092 ,  H01L29/423 ,  H01L27/02 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/306 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L27/0924 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/32139 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/42372 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor substrate includes a plurality of gate electrodes crossing active patterns on a substrate and extending in a second direction, the gate electrodes spaced apart in the second direction from each other, a gate separation pattern having a major axis in the first direction and between two of the gate electrodes, the two of the gate electrodes adjacent to each other in the second direction, and a plurality of gate spacers covering sidewalls of respective ones of the gate electrodes, the gate spacers crossing the gate separation pattern and extending in the second direction. The gate separation pattern includes a lower portion extending in the first direction, an intermediate portion protruding from the lower portion and having a first width, and an upper portion between two adjacent gate spacers and protruding from the intermediate portion, the upper portion having a second width less than the first width.

公开(公告)号：US11107686B2

公开(公告)日：2021-08-31

申请号：US16720878

申请日：2019-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Han Lee ,  Byoung-gi Kim ,  Jong Pil Kim ,  Kihwan Lee

IPC: H01L21/225 ,  H01L21/02 ,  H01L21/8238 ,  H01L23/532 ,  H01L21/762

Abstract: A method for manufacturing a semiconductor device includes performing a first ion implantation process on a substrate to form a lower dopant region in the substrate, patterning the substrate having the lower dopant region to form active patterns, and performing a second ion implantation process on the active patterns to form an upper dopant region in an upper portion of each of the active patterns. The lower and upper dopant regions have a same conductivity type.

公开(公告)号：US10553434B2

公开(公告)日：2020-02-04

申请号：US16027692

申请日：2018-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Han Lee ,  Byoung-gi Kim ,  Jong Pil Kim ,  Kihwan Lee

IPC: H01L21/225 ,  H01L21/02 ,  H01L21/8238 ,  H01L23/532 ,  H01L21/762

Abstract: A method for manufacturing a semiconductor device includes performing a first ion implantation process on a substrate to form a lower dopant region in the substrate, patterning the substrate having the lower dopant region to form active patterns, and performing a second ion implantation process on the active patterns to form an upper dopant region in an upper portion of each of the active patterns. The lower and upper dopant regions have a same conductivity type.