公开(公告)号：US20200321444A1

公开(公告)日：2020-10-08

申请号：US16374330

申请日：2019-04-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yu-Chung LIEN ,  Jiahui YUAN ,  Deepanshu DUTTA

IPC: H01L29/51 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/423 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/28

Abstract: A memory device includes a channel, a control gate electrode, and at least one charge storage element located between the channel and the control gate electrode. The control gate electrode includes a first electrically conductive layer, a second electrically conductive layer and a ferroelectric material layer located between the first electrically conductive layer and the second electrically conductive layer.

公开(公告)号：US20210159169A1

公开(公告)日：2021-05-27

申请号：US16697560

申请日：2019-11-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dengtao ZHAO ,  Zhiping ZHANG ,  Peng ZHANG ,  Deepanshu DUTTA

IPC: H01L23/522 ,  H01L23/528 ,  G11C5/06 ,  G11C16/16 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where the electrically conductive layers comprise word lines located between a source select gate electrode and a drain select gate electrode, a memory opening vertically extending through each layer of the alternating stack to a top surface of the substrate, a memory film and vertical semiconductor channel having a doping of a first conductivity type located in the memory opening, and an active region having a doping of a second conductivity type that is an opposite of the first conductivity type and adjoined to an end portion of the vertical semiconductor channel to provide a p-n junction. The end portion of the vertical semiconductor channel has a first thickness, and a middle portion of the vertical semiconductor channel has a second thickness which is less than the first thickness.

公开(公告)号：US20190304549A1

公开(公告)日：2019-10-03

申请号：US15937420

申请日：2018-03-27

Applicant: SanDisk Technologies LLC

Inventor： Xiang YANG ,  Huai-yuan TSENG ,  Deepanshu DUTTA

IPC: G11C16/30 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/1157

Abstract: An apparatus includes a plurality of solid-state storage elements, a plurality of control lines coupled to the plurality of solid-state storage elements, and control circuitry in communication with the plurality of control lines. The control circuitry is configured to during a first phase of a control line pre-charging stage, charge one or more unselected control lines of the plurality of control lines using a regulated charging current for a period of time based at least in part on a bias variance state associated with the plurality of control lines, and during a second phase of the control line pre-charging stage, charge the one or more unselected bit lines to an inhibit voltage level using an unregulated charging current.