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公开(公告)号：US20230352108A1
公开(公告)日：2023-11-02
申请号：US17733042
申请日：2022-04-29
发明人： Erika Penzo , Henry Chin , Jie Liu , Dong-Il Moon
CPC分类号： G11C16/349 , G11C16/0483 , G11C16/24 , G11C16/26
摘要： An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: acquire a first set of read levels on a wordline of a first block of pages of memory cells; acquire a second set of read levels on a first wordline of a second block of pages of a second set of memory cells in response to determining that the fail bit count of the page after a read operation is above the threshold amount; and acquire a third set of read levels on a second wordline of the second block in response to determining that the fail bit count of the page after the second read operation is above the threshold amount.
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公开(公告)号：US20240177778A1
公开(公告)日：2024-05-30
申请号：US18357436
申请日：2023-07-24
发明人： Yihang Liu , Xiaochen Zhu , Peng Wang , Jie Liu , Lito De La Rama , Feng Gao , Xiaoyu Yang
CPC分类号： G11C16/12 , G11C16/0433 , G11C16/08 , G11C16/3495
摘要： A non-volatile storage apparatus includes non-volatile memory cells, word lines connected to the non-volatile memory cells, and a control circuit connected to the word lines and the memory cells. The word lines include data word lines and dummy word lines. Memory cells connected to data word lines are configured to store host data. Memory cells connected to dummy word lines do not store host data. The control circuit is configured to erase, program and read the memory cells. Errors from threshold voltage up-shifting in the memory cells connected to dummy word lines is prevented by adjusting the voltage applied to dummy word lines.
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公开(公告)号：US20240036740A1
公开(公告)日：2024-02-01
申请号：US17983870
申请日：2022-11-09
发明人： Yihang Liu , Xiaochen Zhu , Jie Liu , Sarath Puthenthermadam , Jiahui Yuan , Feng Gao
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/064 , G06F3/0679
摘要： A non-volatile memory system separately performs a memory operation for multiple sub-blocks of a block in order from previously determined slowest sub-block of the block to a previously determined faster sub-block of the block. As a slower sub-block is more likely to fail, this order of is more likely to identify a failure earlier in the process thereby saving time and reducing potential for a disturb. In some embodiments, the proposed order of operation can be used in conjunction with a programming process that concurrently programs blocks in multiple planes using completion of programming of a fastest plane to a data state as a trigger to test for program failure of other planes to the data state.
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公开(公告)号：US11894080B2
公开(公告)日：2024-02-06
申请号：US17733042
申请日：2022-04-29
发明人： Erika Penzo , Henry Chin , Jie Liu , Dong-Il Moon
CPC分类号： G11C16/349 , G11C16/0483 , G11C16/24 , G11C16/26
摘要： An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: acquire a first set of read levels on a wordline of a first block of pages of memory cells; acquire a second set of read levels on a first wordline of a second block of pages of a second set of memory cells in response to determining that the fail bit count of the page after a read operation is above the threshold amount; and acquire a third set of read levels on a second wordline of the second block in response to determining that the fail bit count of the page after the second read operation is above the threshold amount.
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