公开(公告)号：US20230352108A1

公开(公告)日：2023-11-02

申请号：US17733042

申请日：2022-04-29

Applicant: SanDisk Technologies LLC

Inventor： Erika Penzo ,  Henry Chin ,  Jie Liu ,  Dong-Il Moon

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/349 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26

Abstract: An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: acquire a first set of read levels on a wordline of a first block of pages of memory cells; acquire a second set of read levels on a first wordline of a second block of pages of a second set of memory cells in response to determining that the fail bit count of the page after a read operation is above the threshold amount; and acquire a third set of read levels on a second wordline of the second block in response to determining that the fail bit count of the page after the second read operation is above the threshold amount.

公开(公告)号：US20230410901A1

公开(公告)日：2023-12-21

申请号：US17752524

申请日：2022-05-24

Applicant: SanDisk Technologies LLC

Inventor： Dong-Il Moon ,  Abhijith Prakash ,  Wei Zhao ,  Henry Chin

IPC: G11C11/56 ,  G11C16/26

CPC classification number: G11C11/5642 ,  G11C16/26 ,  G11C11/5671

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the strings and is configured to apply a read voltage to a selected ones of the plurality of word lines during a read operation and ramp down to a discharge voltage at an end of the read operation and apply a ready voltage to the selected ones of the plurality of word lines during a ready period of time following the read operation. The control means is also configured to adjust at least one of the discharge voltage and the ready voltage based on a temperature of the memory apparatus.

公开(公告)号：US12046314B2

公开(公告)日：2024-07-23

申请号：US17897993

申请日：2022-08-29

Applicant: SanDisk Technologies LLC

Inventor： Abu Naser Zainuddin ,  Jiahui Yuan ,  Dong-Il Moon

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C29/12 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: G11C29/12005 ,  G06F3/0625 ,  G06F3/0653 ,  G06F3/0679 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3459 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  G11C2029/1202 ,  H01L2224/08145 ,  H01L2225/06506 ,  H01L2225/06562

Abstract: To reduce spikes in the current used by a NAND memory die, different ramp rates are used for the pass voltage applied to unselected word lines during a program operation depending on whether data is stored in a multi-level cell (MLC) format or in a single level cell (SLC) format. These ramp rates can be determined through device characterization and stored as parameter values on the memory die. Different ramp rate interval values can also be used for the pass voltage applied to unselected word lines during a program operation depending on whether data is stored in an MLC format or in an SLC format.

公开(公告)号：US11894080B2

公开(公告)日：2024-02-06

申请号：US17733042

申请日：2022-04-29

Applicant: SanDisk Technologies LLC

Inventor： Erika Penzo ,  Henry Chin ,  Jie Liu ,  Dong-Il Moon

IPC: G11C16/06 ,  G11C16/34 ,  G11C16/26 ,  G11C16/24 ,  G11C16/04

CPC classification number: G11C16/349 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26

Abstract: An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: acquire a first set of read levels on a wordline of a first block of pages of memory cells; acquire a second set of read levels on a first wordline of a second block of pages of a second set of memory cells in response to determining that the fail bit count of the page after a read operation is above the threshold amount; and acquire a third set of read levels on a second wordline of the second block in response to determining that the fail bit count of the page after the second read operation is above the threshold amount.

公开(公告)号：US11894051B2

公开(公告)日：2024-02-06

申请号：US17752524

申请日：2022-05-24

Applicant: SanDisk Technologies LLC

Inventor： Dong-Il Moon ,  Abhijith Prakash ,  Wei Zhao ,  Henry Chin

IPC: G11C7/00 ,  G11C11/56 ,  G11C16/26

CPC classification number: G11C11/5642 ,  G11C11/5671 ,  G11C16/26

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the strings and is configured to apply a read voltage to a selected ones of the plurality of word lines during a read operation and ramp down to a discharge voltage at an end of the read operation and apply a ready voltage to the selected ones of the plurality of word lines during a ready period of time following the read operation. The control means is also configured to adjust at least one of the discharge voltage and the ready voltage based on a temperature of the memory apparatus.