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公开(公告)号：US20230352108A1
公开(公告)日：2023-11-02
申请号：US17733042
申请日：2022-04-29
发明人： Erika Penzo , Henry Chin , Jie Liu , Dong-Il Moon
CPC分类号： G11C16/349 , G11C16/0483 , G11C16/24 , G11C16/26
摘要： An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: acquire a first set of read levels on a wordline of a first block of pages of memory cells; acquire a second set of read levels on a first wordline of a second block of pages of a second set of memory cells in response to determining that the fail bit count of the page after a read operation is above the threshold amount; and acquire a third set of read levels on a second wordline of the second block in response to determining that the fail bit count of the page after the second read operation is above the threshold amount.
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公开(公告)号：US11854620B2
公开(公告)日：2023-12-26
申请号：US17351533
申请日：2021-06-18
发明人： Erika Penzo , Han-Ping Chen , Henry Chin
CPC分类号： G11C16/08 , G11C11/5628 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/3459 , H10B41/27 , H10B43/27
摘要： An apparatus is provided that includes a plurality of word lines that include a plurality of word line zones, a plurality of non-volatile memory cells coupled to the plurality of word lines, and a control circuit coupled to the non-volatile memory cells. The control circuit is configured to determine a corresponding initial program voltage for each of the word line zones. Each corresponding initial program voltage is determined based on a number of program erase cycles.
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公开(公告)号：US20230066972A1
公开(公告)日：2023-03-02
申请号：US17410265
申请日：2021-08-24
发明人： Yu-Chung Lien , Henry Chin , Erika Penzo
摘要： A memory device that includes a plurality of memory cells arranged in an array is provided. A control circuitry is configured to program a single bit of data in each memory cell of the plurality of memory cells. The control circuitry is further configured to program a first set of memory cells of the plurality of memory cells using a first programming operation that includes a single programming pulse and no verify pulse and program a second set of memory cells of the plurality of memory cells using a second programming operation that includes at least one programming loop with a programming pulse and a verify pulse.
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公开(公告)号：US20220406380A1
公开(公告)日：2022-12-22
申请号：US17351533
申请日：2021-06-18
发明人： Erika Penzo , Han-Ping Chen , Henry Chin
摘要： An apparatus is provided that includes a plurality of word lines that include a plurality of word line zones, a plurality of non-volatile memory cells coupled to the plurality of word lines, and a control circuit coupled to the non-volatile memory cells. The control circuit is configured to determine a corresponding initial program voltage for each of the word line zones. Each corresponding initial program voltage is determined based on a number of program erase cycles.
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公开(公告)号：US12057161B2
公开(公告)日：2024-08-06
申请号：US17847698
申请日：2022-06-23
发明人： Wei Zhao , Dong-II Moon , Erika Penzo , Henry Chin
CPC分类号： G11C11/5642 , G11C11/5628 , G11C11/5671 , G11C16/10 , G11C16/26
摘要： The memory device includes a plurality of memory blocks that can individually operate in either a multi-bit per memory cell mode or a single-bit per memory cell mode. Certain voltage parameters during programming and reading are shared between these two operating modes, and certain voltage parameters are unique to each operating mode. One unique voltage parameter is a pass voltage VREADK that is applied to word lines adjacent a selected word line being read. Another unique voltage parameter is a VSGD voltage that is applied to a select gate drain transistor during programming. Yet another unique voltage parameter is an inhibit voltage that is applied to a bit line coupled with a memory cell being inhibited from programming while other memory cells are programmed.
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公开(公告)号：US20230420042A1
公开(公告)日：2023-12-28
申请号：US17847698
申请日：2022-06-23
发明人： Wei Zhao , Dong-II Moon , Erika Penzo , Henry Chin
CPC分类号： G11C11/5642 , G11C11/5628 , G11C11/5671 , G11C16/10 , G11C16/26
摘要： The memory device includes a plurality of memory blocks that can individually operate in either a multi-bit per memory cell mode or a single-bit per memory cell mode. Certain voltage parameters during programming and reading are shared between these two operating modes, and certain voltage parameters are unique to each operating mode. One unique voltage parameter is a pass voltage VREADK that is applied to word lines adjacent a selected word line being read. Another unique voltage parameter is a VSGD voltage that is applied to a select gate drain transistor during programming. Yet another unique voltage parameter is an inhibit voltage that is applied to a bit line coupled with a memory cell being inhibited from programming while other memory cells are programmed.
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7.发明公开公开(公告)号：US20240212737A1
公开(公告)日：2024-06-27
申请号：US18222708
申请日：2023-07-17
发明人： Dong-il Moon , Erika Penzo , Henry Chin
IPC分类号： G11C11/406 , G11C11/408
CPC分类号： G11C11/40615 , G11C11/4085 , G11C11/4087
摘要： A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes each comprising a channel. The memory cells retain a threshold voltage and are operable in one of a first read condition in which a word line voltage of the word lines is discharged and a second read condition in which the word line voltage of the word lines is coupled up to a residual voltage level. A control means is configured to apply a predetermined refresh read voltage to the word lines at predetermined intervals of time during a refresh read operation to maintain the memory cells in the second read condition. The control means also adjusts a read setup time in which the word lines are ramped up and the channel is discharged during a read operation based on occurrences of the refresh read operation.
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公开(公告)号：US20240071524A1
公开(公告)日：2024-02-29
申请号：US17895412
申请日：2022-08-25
发明人： Xiang Yang , Henry Chin , Erika Penzo , Muhammad Masuduzzaman
CPC分类号： G11C16/3459 , G11C16/102 , G11C16/14 , G11C16/3404
摘要： Technology is disclosed herein for smart verify in a memory system that has a four bit per cell program mode (or X4 mode) and also a three bit per cell program mode (or X3 mode). The X3 mode uses a three-bit gray code that is based on a four-bit gray code of the X4 mode. The memory system skips verify of states in the X3 mode, while using a considerable portion of the programming logic from the X4 mode. In one X3 mode the memory system skips B-state verify while the number of memory cells having a Vt above an A-state verify voltage is below a threshold. In one X3 mode the memory system determines whether to skip verify for a first set of data states based on a first test and determines whether to skip verify for a second set of data states based on a second test.
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公开(公告)号：US11894080B2
公开(公告)日：2024-02-06
申请号：US17733042
申请日：2022-04-29
发明人： Erika Penzo , Henry Chin , Jie Liu , Dong-Il Moon
CPC分类号： G11C16/349 , G11C16/0483 , G11C16/24 , G11C16/26
摘要： An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: acquire a first set of read levels on a wordline of a first block of pages of memory cells; acquire a second set of read levels on a first wordline of a second block of pages of a second set of memory cells in response to determining that the fail bit count of the page after a read operation is above the threshold amount; and acquire a third set of read levels on a second wordline of the second block in response to determining that the fail bit count of the page after the second read operation is above the threshold amount.
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公开(公告)号：US20220392551A1
公开(公告)日：2022-12-08
申请号：US17336936
申请日：2021-06-02
发明人： Hua-Ling Hsu , Henry Chin , Han-Ping Chen , Erika Penzo , Fanglin Zhang
摘要： Apparatus and methods are described to program memory cells and control bit line discharge schemes during programming based on the data pattern. The memory controller can predict program data pattern based on SLC pulse number and TLC data completion signals and use these signals to adjust when the inhibited bit lines can discharge. Once a TLC program operation have more one data, the memory controller will enable EQVDDSA_PROG to equalize to VDDSA, and then discharge. In SLC program, the memory controller will enable EQVDDSA_PROG only in first program pulse and disable it thereafter.
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