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    In-place write techniques without erase in a memory device
    2.
    发明授权
    In-place write techniques without erase in a memory device 有权

    公开(公告)号：US12243591B2

    公开(公告)日：2025-03-04

    申请号：US17896587

    申请日：2022-08-26

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Jiacen Guo ,  Takayuki Inoue

    IPC: G11C7/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/34

    Abstract: The memory device includes a plurality of memory blocks, each including a plurality of memory cells arranged in a plurality of word lines. Control circuitry is in communication with the plurality of memory blocks. In operation, the control circuitry receives a data write instruction and programs the memory cells of the memory blocks to a one bit per memory cell (SLC) format. In response to the data programmed to the memory cells of the memory blocks in the SLC format reaching an SLC limit prior to completion of the data write instruction, without erasing the memory cells programmed to the SLC format, the control circuitry programs the memory cells of at least some of the plurality of memory blocks from the SLC format to a two bits per memory cell (MLC) format.

    IN-PLACE WRITE TECHNIQUES WITHOUT ERASE IN A MEMORY DEVICE
    4.
    发明公开
    IN-PLACE WRITE TECHNIQUES WITHOUT ERASE IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240071508A1

    公开(公告)日：2024-02-29

    申请号：US17896587

    申请日：2022-08-26

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Jiacen Guo ,  Takayuki Inoue

    IPC: G11C16/10 ,  G11C16/08 ,  G11C16/14 ,  G11C16/34

    CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/14 ,  G11C16/3459

    Abstract: The memory device includes a plurality of memory blocks, each including a plurality of memory cells arranged in a plurality of word lines. Control circuitry is in communication with the plurality of memory blocks. In operation, the control circuitry receives a data write instruction and programs the memory cells of the memory blocks to a one bit per memory cell (SLC) format. In response to the data programmed to the memory cells of the memory blocks in the SLC format reaching an SLC limit prior to completion of the data write instruction, without erasing the memory cells programmed to the SLC format, the control circuitry programs the memory cells of at least some of the plurality of memory blocks from the SLC format to a two bits per memory cell (MLC) format.

    MLC programming techniques in a memory device
    5.
    发明授权
    MLC programming techniques in a memory device 有权

    公开(公告)号：US12205654B2

    公开(公告)日：2025-01-21

    申请号：US17690713

    申请日：2022-03-09

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Takayuki Inoue ,  Jiacen Guo

    IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

    Abstract: The memory device includes a plurality of memory cells which are arranged in an array. The memory device further includes a plurality of bit lines that are coupled with the memory cells and a controller. The controller is configured to program the memory cells from an erased data state to three programmed data states in a programming operation that includes three programming pulses and zero verify operations using different patterns to dictate the application of inhibit voltages to the bit lines during each of the three programming pulses. The patterns include two pre-established patterns and additional patterns that are derived from the pre-established patterns using logic operations.

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