Independent state completion for each plane during flash memory programming

    公开(公告)号:US10134474B1

    公开(公告)日:2018-11-20

    申请号:US15789095

    申请日:2017-10-20

    Inventor: Yi-Chieh Chen

    Abstract: An apparatus includes a first plane of memory cells including an associated first buffer, a second plane of memory cells including an associated second buffer. The apparatus also includes a controller configured to transfer data corresponding to a first memory state the first buffer and transfer data corresponding to a second memory state to the second buffer. The apparatus also includes state machine configured to apply program pulses to the first and second planes of memory cells. The apparatus also includes read/write circuitry configured to independently confirm that the first and second planes of memory cells have reached the first and second memory states.

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