公开(公告)号：US10468459B2

公开(公告)日：2019-11-05

申请号：US15854563

申请日：2017-12-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yusuke Oda ,  Michiaki Sano

IPC: H01L27/24 ,  H01L45/00 ,  G06F11/10 ,  G11C13/00 ,  G11C29/52

Abstract: Systems and methods for implementing a memory array comprising vertical bit lines that are connected to different pairs of vertical thin-film transistors (TFTs) are described. A set of vertical TFTs may be formed such that a first TFT and a second TFT are spaced apart by a first separation distance and a third TFT and the second TFT are spaced apart by a second separation distance. The fabrication of the memory array includes forming a layer of conducting material with a thickness that is greater than half of the first separation distance and less than half of the second separation distance and then performing an anisotropic etch to remove portions of the conducting material such that openings in the conducting material are formed between the pairs of vertical TFTs while preventing openings from forming between the vertical TFTs of each pair of vertical TFTs.

公开(公告)号：US20190198568A1

公开(公告)日：2019-06-27

申请号：US15854563

申请日：2017-12-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yusuke Oda ,  Michiaki Sano

IPC: H01L27/24 ,  H01L45/00

Abstract: Systems and methods for implementing a memory array comprising vertical bit lines that are connected to different pairs of vertical thin-film transistors (TFTs) are described. A set of vertical TFTs may be formed such that a first TFT and a second TFT are spaced apart by a first separation distance and a third TFT and the second TFT are spaced apart by a second separation distance. The fabrication of the memory array includes forming a layer of conducting material with a thickness that is greater than half of the first separation distance and less than half of the second separation distance and then performing an anisotropic etch to remove portions of the conducting material such that openings in the conducting material are formed between the pairs of vertical TFTs while preventing openings from forming between the vertical TFTs of each pair of vertical TFTs.

公开(公告)号：US09754999B1

公开(公告)日：2017-09-05

申请号：US15240998

申请日：2016-08-18

Applicant: SanDisk Technologies LLC

Inventor： Seje Takaki ,  Manabu Hayashi ,  Ryousuke Itou ,  Takuro Maede ,  Kengo Kajiwara ,  Tetsuya Yamada ,  Yusuke Oda

IPC: H01L27/11551 ,  H01L27/24 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L27/2454 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/249 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

Abstract: A method is provided that includes forming a transistor by forming a gate disposed in a first direction above a substrate, the gate including a first bridge portion and a second bridge portion, forming the first bridge portion extending in the first direction and disposed near a top of the gate, and forming the second bridge portion extending in the first direction and disposed near a bottom of the gate.