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6 条记录 (耗时 0.026 秒)

    Integration of non-noble DRAM electrode
    1.
    发明授权
    Integration of non-noble DRAM electrode 有权
    非贵重DRAM电极的集成

    公开(公告)号：US08530348B1

    公开(公告)日：2013-09-10

    申请号：US13482573

    申请日：2012-05-29

    申请人： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Edward L. Haywood ,  Hiroyuki Ode ,  Gerald Richardson

    发明人： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Edward L. Haywood ,  Hiroyuki Ode ,  Gerald Richardson

    IPC分类号： H01L21/4763

    CPC分类号： H01L29/92 ,  H01L28/75 ,  H01L28/92

    摘要： A method for forming a capacitor stack is described. In some embodiments of the present invention, a first electrode structure is comprised of multiple materials. A first material is formed above the substrate. A portion of the first material is etched. A second material is formed above the first material. A portion of the second material is etched. Optionally, the first electrode structure receives an anneal treatment. A dielectric material is formed above the first electrode structure. Optionally, the dielectric material receives an anneal treatment. A second electrode material is formed above the dielectric material. Typically, the capacitor stack receives an anneal treatment.

    摘要翻译： 描述形成电容器堆叠的方法。 在本发明的一些实施例中，第一电极结构由多种材料构成。 在基板上方形成第一材料。 蚀刻第一材料的一部分。 在第一材料上方形成第二材料。 蚀刻第二材料的一部分。 可选地，第一电极结构接受退火处理。 介电材料形成在第一电极结构之上。 可选地，电介质材料接受退火处理。 在电介质材料上方形成第二电极材料。 通常，电容器堆叠接收退火处理。

    Enhanced non-noble electrode layers for DRAM capacitor cell
    2.
    发明授权
    Enhanced non-noble electrode layers for DRAM capacitor cell 有权
    用于DRAM电容器电池的增强型非贵金属电极层

    公开(公告)号：US08647943B2

    公开(公告)日：2014-02-11

    申请号：US13494693

    申请日：2012-06-12

    申请人： Hanhong Chen ,  Wim Y. Deweerd ,  Edward L Haywood ,  Sandra G Malhotra ,  Hiroyuki Ode

    发明人： Hanhong Chen ,  Wim Y. Deweerd ,  Edward L Haywood ,  Sandra G Malhotra ,  Hiroyuki Ode

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/60 ,  H01L28/75

    摘要： A metal oxide first electrode material for a MIM DRAM capacitor is formed wherein the first and/or second electrode materials or structures contain layers having one or more dopants up to a total doping concentration that will not prevent the electrode materials from crystallizing during a subsequent anneal step. Advantageously, the electrode doped with one or more of the dopants has a work function greater than about 5.0 eV. Advantageously, the electrode doped with one or more of the dopants has a resistivity less than about 1000 μΩ cm. Advantageously, the electrode materials are conductive molybdenum oxide.

    摘要翻译： 形成用于MIM DRAM电容器的金属氧化物第一电极材料，其中第一和/或第二电极材料或结构包含具有一个或多个掺杂剂的层，直到总掺杂浓度，其将不会阻止电极材料在随后的退火期间结晶 步。 有利地，掺杂有一种或多种掺杂剂的电极具有大于约5.0eV的功函数。 有利地，掺杂有一种或多种掺杂剂的电极具有小于约1000μΩmΩ的电阻率。 有利地，电极材料是导电性氧化钼。

    Leakage reduction in DRAM MIM capacitors
    3.
    发明申请
    Leakage reduction in DRAM MIM capacitors 有权

    公开(公告)号：US20140080282A1

    公开(公告)日：2014-03-20

    申请号：US13621910

    申请日：2012-09-18

    申请人： Tony P. Chiang ,  Wim Y. Deweerd ,  Sandra G. Malhotra

    发明人： Tony P. Chiang ,  Wim Y. Deweerd ,  Sandra G. Malhotra

    IPC分类号： H01L21/02

    CPC分类号： H01L29/92 ,  H01L27/10852 ,  H01L28/40

    摘要： A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high-k phase of a subsequently deposited dielectric layer. The high-k dielectric layer includes a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.