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公开(公告)号：US20060053190A1
公开(公告)日：2006-03-09
申请号：US10937693
申请日：2004-09-09
IPC分类号： G06F7/38
摘要： An apparatus, a method, and a computer program are provided for anticipating leading zeros for a Floating Point (FP) computation. Traditional leading zero anticipators (LZA) are typically very wide. To reduce the width of the LZA, it is subdivided to two smaller LZA that compute edge vectors for the most and least significant bits of intermediate resultant vectors. Therefore, a LZA can be easily folded to reduce the area requirement so as to increase the versatility of the LZA.
摘要翻译： 提供了一种装置，方法和计算机程序，用于预测浮点（FP）计算的前导零。 传统领先的零预期（LZA）通常非常广泛。 为了减小LZA的宽度，它被细分为两个较小的LZA，它们计算中间合成向量的最高有效位和最低有效位的边缘向量。 因此，LZA可以容易地折叠以减小面积要求，从而增加LZA的通用性。
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公开(公告)号：US07245159B2
公开(公告)日：2007-07-17
申请号：US10891771
申请日：2004-07-15
IPC分类号： H03K19/20
CPC分类号： H03K17/223 , H03K17/005
摘要： A method, a computer program, and an apparatus are provided to protect transmission gates in a multiplexer (mux). Because transmission gates are much faster than the more convention AND-OR arrays, transmission gate usage in muxes are being used more often in high speed circuitry. However, transmission gate have a significant problem in that short circuit are possible for situations where there is not a one-hot select signal. Therefore, to eliminate the problem, logic gates are utilized specifically during Power-On Reset (POR) to force a one-hot selection to prevent any possible short circuits.
摘要翻译： 提供了一种方法，计算机程序和装置来保护复用器（多路复用器）中的传输门。 因为传输门比更常规的AND-OR阵列快得多，所以在高速电路中更频繁地使用多路复用器中的传输门使用。 然而，传输门具有显着的问题，即在没有单热选择信号的情况下短路是可能的。 因此，为了消除这个问题，在上电复位（POR）期间特别使用逻辑门来强制单热选择以防止任何可能的短路。
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3.发明授权Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units 失效用于在单指令多数据（SIMD）浮点单元中控制舍入模式的装置公开(公告)号：US07447725B2
公开(公告)日：2008-11-04
申请号：US10982110
申请日：2004-11-05
IPC分类号： G06F7/38
CPC分类号： G06F7/49947 , G06F7/483 , G06F7/49968 , G06F7/49973 , G06F7/49989 , G06F2207/3828
摘要： An apparatus for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.
摘要翻译： 公开了一种用于在单指令多数据（SIMD）浮点单元中控制舍入模式的装置。 SIMD浮点单元包括具有第一舍入模式位字段和第二舍入模式位字段的浮点状态和控制寄存器（FPSCR）。 SIMD浮点单元还包括用于生成第一切片和第二切片的装置。 在浮点运算期间，SIMD浮点单元根据第一舍入模式位字段中的位并且在第二舍入中的位同时对第一切片进行第一舍入运算，并对第二切片进行第二舍入运算 FPSCR中的模式位字段。
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4.发明授权Method for controlling rounding modes in single instruction multiple data (SIMD) floating-point units 有权用于控制单指令多数据（SIMD）浮点单元中舍入模式的方法公开(公告)号：US08229989B2
公开(公告)日：2012-07-24
申请号：US12238500
申请日：2008-09-26
IPC分类号： G06F7/38
CPC分类号： G06F7/49947 , G06F7/483 , G06F7/49968 , G06F7/49973 , G06F7/49989 , G06F2207/3828
摘要： A method for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.
摘要翻译： 公开了一种用于在单指令多数据（SIMD）浮点单元中控制舍入模式的方法。 SIMD浮点单元包括具有第一舍入模式位字段和第二舍入模式位字段的浮点状态和控制寄存器（FPSCR）。 SIMD浮点单元还包括用于生成第一切片和第二切片的装置。 在浮点运算期间，SIMD浮点单元根据第一舍入模式位字段中的位并且在第二舍入中的位同时对第一切片进行第一舍入运算，并对第二切片进行第二舍入运算 FPSCR中的模式位字段。
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公开(公告)号：US08166085B2
公开(公告)日：2012-04-24
申请号：US12105726
申请日：2008-04-18
CPC分类号： G06F5/012
摘要： The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a bit group of the shift amount is employable to affect at least one of the plurality of shift stages, thereby decreasing processing time.
摘要翻译： 本发明提供了作为多个数字的函数的移位量的计算。 至少一个解码器和至少一个加法器并联耦合。 移位器被配置为计算多个移位级中的值，并且其中移位量的位组可用于影响多个移位级中的至少一个，从而减少处理时间。
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6.发明授权公开(公告)号：US07392270B2
公开(公告)日：2008-06-24
申请号：US10902475
申请日：2004-07-29
CPC分类号： G06F5/012
摘要： The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a bit group of the shift amount is employable to affect at least one of the plurality of shift stages, thereby decreasing processing time.
摘要翻译： 本发明提供了作为多个数字的函数的移位量的计算。 至少一个解码器和至少一个加法器并联耦合。 移位器被配置为计算多个移位级中的值，并且其中移位量的位组可用于影响多个移位级中的至少一个，从而减少处理时间。
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公开(公告)号：US20080195684A1
公开(公告)日：2008-08-14
申请号：US12105726
申请日：2008-04-18
IPC分类号： G06F7/00
CPC分类号： G06F5/012
摘要： The present invention provides for calculating a shift amount as a function of a plurality of numbers. At least one decoder and the at least one adder are coupled in parallel. A shifter is configured to compute a value in a plurality of shift stages, and wherein a bit group of the shift amount is employable to affect at least one of the plurality of shift stages, thereby decreasing processing time.
摘要翻译： 本发明提供了作为多个数字的函数的移位量的计算。 至少一个解码器和至少一个加法器并联耦合。 移位器被配置为计算多个移位级中的值，并且其中移位量的位组可用于影响多个移位级中的至少一个，从而减少处理时间。
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8.发明申请Method for Controlling Rounding Modes in Single Instruction Multiple Data (SIMD) Floating-Point Units 有权用于控制单指令多数据（SIMD）浮点单元中舍入模式的方法公开(公告)号：US20090024684A1
公开(公告)日：2009-01-22
申请号：US12238500
申请日：2008-09-26
IPC分类号： G06F7/483
CPC分类号： G06F7/49947 , G06F7/483 , G06F7/49968 , G06F7/49973 , G06F7/49989 , G06F2207/3828
摘要： A method for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.
摘要翻译： 公开了一种用于在单指令多数据（SIMD）浮点单元中控制舍入模式的方法。 SIMD浮点单元包括具有第一舍入模式位字段和第二舍入模式位字段的浮点状态和控制寄存器（FPSCR）。 SIMD浮点单元还包括用于生成第一切片和第二切片的装置。 在浮点运算期间，SIMD浮点单元根据第一舍入模式位字段中的位并且在第二舍入中的位同时对第一切片进行第一舍入运算，并对第二切片进行第二舍入运算 FPSCR中的模式位字段。
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公开(公告)号：US07406589B2
公开(公告)日：2008-07-29
申请号：US11127848
申请日：2005-05-12
申请人： Sang Hoo Dhong , Gordon Clyde Fossum , Harm Peter Hofstee , Brad William Michael , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Gordon Clyde Fossum , Harm Peter Hofstee , Brad William Michael , Silvia Melitta Mueller , Hwa-Joon Oh
CPC分类号： G06F7/483 , G06F7/535 , G06F7/5443 , G06F7/5525 , G06F9/30014 , G06F2207/5356
摘要： High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.
摘要翻译： 高精度浮点函数估计分为两个指令：低精度表查找指令和线性插值指令。 可以使用该方案来实现不同功能的估计：为每个不同的功能提供单独的表查找指令，而仅需要单个插补指令，因为单个内插指令可以执行任何功能的内插步骤 估计。 因此，与专用硬件相比，产生的开销大大降低，同时仍保持统一的FPU延迟，这允许更简单的控制逻辑。
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公开(公告)号：US07237163B2
公开(公告)日：2007-06-26
申请号：US10982111
申请日：2004-11-05
IPC分类号： G01R31/28
CPC分类号： G06F11/267 , G01R31/3008
摘要： An apparatus, a method and a computer program are provided to reduce leakage current in a processor. Traditionally, extra logic is employed to reduce leakage currents. However, reducing leakage current without sacrificing fine grain operations and speed can be difficult. Achieving such a goal can be accomplished by incorporating a multiplexer (mux) into the scan-in path of scan registers so that units or sub-units of the processor can be powered down individually. Additionally, the muxes are not incorporated into time paths, so speed can be preserved.
摘要翻译： 提供了一种装置，方法和计算机程序以减少处理器中的泄漏电流。 传统上，采用额外的逻辑来减少漏电流。 然而，减少泄漏电流而不牺牲精细的晶粒操作和速度可能是困难的。 可以通过将多路复用器（多路复用器）复用到扫描寄存器的扫描路径中来实现这一目标，从而可以单独关闭处理器的单元或子单元。 此外，多路复用器并不并入时间路径，因此可以保留速度。
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