公开(公告)号：US20180337742A1

公开(公告)日：2018-11-22

申请号：US15596753

申请日：2017-05-16

申请人： Sang Il PARK

发明人： Sang Il PARK

IPC分类号： H04H20/57 ,  H04H20/72 ,  H04L29/06 ,  H04W84/12

摘要： An apparatus for sharing terrestrial broadcast contents by using a smart antenna configured to receive the terrestrial broadcast contents and to transmit received terrestrial broadcast contents to a display terminal via a wireless communication network and a display terminal configured to receive the terrestrial broadcast contents from the smart antenna and to display received terrestrial broadcast contents includes a smart antenna searching unit configured to search at least one other smart antenna connected via a network, a contents searching unit configured to search terrestrial broadcast contents receivable by the at least one other smart antenna, and a contents sharing unit configured to cause the terrestrial broadcast contents searched by the contents searching unit to be shared by at least one display terminal.

公开(公告)号：US20120275247A1

公开(公告)日：2012-11-01

申请号：US13191625

申请日：2011-07-27

申请人： Sun Young HWANG ,  Sang Il PARK

发明人： Sun Young HWANG ,  Sang Il PARK

IPC分类号： G11C29/04

CPC分类号： G11C29/4401 ,  G11C29/789

摘要： A semiconductor memory device includes a latch address generation unit configured to latch row addresses to generate first and second latch addresses when at least one of memory cells coupled to sub word lines is faulty, wherein the first and second latch addresses select different main word lines, and a repair unit configured to perform a repair operation on memory cells coupled to the main word lines selected by the first and second latch addresses.

摘要翻译： 半导体存储器件包括锁存地址生成单元，其被配置为当耦合到子字线的存储器单元中的至少一个有故障时，锁存行地址以产生第一和第二锁存器地址，其中第一和第二锁存器地址选择不同的主字线， 以及修复单元，被配置为对与由第一和第二锁存器地址选择的主字线耦合的存储器单元执行修复操作。

公开(公告)号：US20100018574A1

公开(公告)日：2010-01-28

申请号：US12568360

申请日：2009-09-28

申请人： Seong Won KWON ,  Joong Hwan KWAK ,  Sang Il PARK ,  Yang Ji Hwan ,  Sang Hwan Kim ,  Yoo Jin Lee ,  Jin Koog Shin ,  Koeng Su Lim

发明人： Seong Won KWON ,  Joong Hwan KWAK ,  Sang Il PARK ,  Yang Ji Hwan ,  Sang Hwan Kim ,  Yoo Jin Lee ,  Jin Koog Shin ,  Koeng Su Lim

IPC分类号： H01L31/0224 ,  H01L31/18

CPC分类号： H01L31/1804 ,  H01L31/022466 ,  H01L31/046 ,  H01L31/0463 ,  H01L31/1884 ,  Y02E10/547 ,  Y02P70/521

摘要： Provided are an integrated thin-film solar cell and a method of manufacturing the same. The method comprises forming and patterning a conductive material to be adjacently spaced a predetermined distance apart from each other on a substrate; forming a solar cell (semiconductor) layer on the resultant substrate; obliquely depositing a first transparent conductive material on the solar cell layer; etching the solar cell layer using the first transparent conductive material as a mask; and obliquely depositing a second transparent conductive material on the resultant substrate, and electrically connecting the conductive material with the first transparent conductive material.

摘要翻译： 提供一种集成薄膜太阳能电池及其制造方法。 该方法包括在衬底上形成和图案化彼此相隔预定距离的导电材料; 在所得基板上形成太阳能电池（半导体）层; 将第一透明导电材料倾斜地沉积在太阳能电池层上; 使用第一透明导电材料作为掩模蚀刻太阳能电池层; 并在所得基板上倾斜沉积第二透明导电材料，并将导电材料与第一透明导电材料电连接。

公开(公告)号：US20130121097A1

公开(公告)日：2013-05-16

申请号：US13411551

申请日：2012-03-03

申请人： Sang Il PARK

发明人： Sang Il PARK

IPC分类号： G11C29/04

CPC分类号： G11C29/76 ,  G11C29/34 ,  G11C2029/1202

摘要： A semiconductor memory device includes a signal generation unit configured to generate a toggling signal and first and second pulse signals in response to a test signal and a burst pulse signal. An address output unit may be configured to receive first to fourth input addresses and output sequentially first to fourth output addresses in response to the toggling signal and the first and second pulse signals. A repair unit may be configured to perform a repair operation on a word line selected by the first to fourth output addresses.

摘要翻译： 半导体存储器件包括：信号生成单元，被配置为响应于测试信号和突发脉冲信号产生切换信号和第一和第二脉冲信号。 地址输出单元可以被配置为响应于切换信号和第一和第二脉冲信号而接收第一至第四输入地址并且顺序地输出第一至第四输出地址。 维修单元可以被配置为对由第一至第四输出地址选择的字线执行修复操作。

公开(公告)号：US20110242929A1

公开(公告)日：2011-10-06

申请号：US12845568

申请日：2010-07-28

申请人： Sun Mo AN ,  Sang Il PARK

发明人： Sun Mo AN ,  Sang Il PARK

IPC分类号： G11C8/04

CPC分类号： G11C11/40611 ,  G11C2211/4068

摘要： A semiconductor memory apparatus includes a counting control circuit and an address counting circuit. The counting control circuit is configured to generate a first counting start signal, a second counting start signal and a counting count signal in response to an auto-refresh signal, a voltage stabilization signal and a fuse control signal. The address counting circuit is configured to count a plurality of count addresses in response to the first counting start signal, and to count one or more specified count addresses from among the plurality of count addresses in response to the second counting start signal and the counting control signal.

摘要翻译： 半导体存储装置包括计数控制电路和地址计数电路。 计数控制电路被配置为响应于自动刷新信号，电压稳定信号和熔丝控制信号产生第一计数开始信号，第二计数开始信号和计数计数信号。 地址计数电路被配置为响应于第一计数开始信号对多个计数地址进行计数，并且响应于第二计数开始信号和计数控制对多个计数地址中的一个或多个指定的计数地址进行计数 信号。

公开(公告)号：US20120195150A1

公开(公告)日：2012-08-02

申请号：US13191687

申请日：2011-07-27

申请人： Sang Il PARK

发明人： Sang Il PARK

IPC分类号： G11C11/402

CPC分类号： G11C11/40618 ,  G11C11/408

摘要： A refresh circuit includes an enable pulse generator configured to generate a first enable pulse and a second enable pulse, a first address latch configured to latch the first row address in synchronization with the first enable pulse and generate a first latch address, and a second address latch configured to latch a second row address in synchronization with the second enable pulse and generate second and third latch addresses.

摘要翻译： 刷新电路包括配置用于产生第一使能脉冲和第二使能脉冲的使能脉冲发生器，配置成与第一使能脉冲同步地锁存第一行地址并产生第一锁存器地址的第一地址锁存器，以及第二地址 锁存器被配置为与第二使能脉冲同步地锁存第二行地址并产生第二和第三锁存器地址。

公开(公告)号：US20120008427A1

公开(公告)日：2012-01-12

申请号：US13241587

申请日：2011-09-23

申请人： Sang Il PARK

发明人： Sang Il PARK

IPC分类号： G11C7/10 ,  G11C5/14

CPC分类号： G11C8/14 ,  G11C5/147 ,  G11C7/22 ,  G11C2207/2227

摘要： A semiconductor memory device capable of reducing off-current in a standby mode is provided. The semiconductor memory device includes an enable signal generating unit configured to receive a plurality of address decoding signals and generate a first enable signal to select a first cell block and a second enable signal to select a second cell block, and an internal voltage generating unit for generating an internal voltage by controlling a supply of a first voltage in accordance with the first or second enable signals.

摘要翻译： 提供能够在待机模式下减少截止电流的半导体存储器件。 半导体存储器件包括：使能信号生成单元，被配置为接收多个地址解码信号，并产生第一使能信号以选择第一单元块和第二使能信号以选择第二单元块;以及内部电压产生单元， 通过根据第一或第二使能信号控制第一电压的供应来产生内部电压。

公开(公告)号：US20130322496A1

公开(公告)日：2013-12-05

申请号：US13483814

申请日：2012-05-30

申请人： Sang Il PARK ,  O Bong KWON

发明人： Sang Il PARK ,  O Bong KWON

IPC分类号： H04B1/38

CPC分类号： H04N21/6175 ,  H04N7/17309 ,  H04N21/235 ,  H04N21/23614 ,  H04N21/41407 ,  H04N21/435 ,  H04N21/436 ,  H04N21/44227 ,  H04N21/4622 ,  H04N21/4782 ,  H04N21/485 ,  H04N21/6187 ,  H04N21/6334 ,  H04N21/6582

摘要： The present invention relates to a method for securing indirect return channel and mobile digital broadcast receiver, and more particularly, to a method for securing the indirect return channel for mobile digital broadcast receiver without internal Internet access capabilities by enabling indirect access to Internet using external Internet devices having internal Internet access capabilities, and a mobile digital broadcast receiver securing indirect return channel using external Internet devices with internal Internet access capabilities.

摘要翻译： 本发明涉及一种用于确保间接返回信道和移动数字广播接收机的方法，更具体地，涉及一种用于通过使用外部互联网间接访问因特网来保护具有内部因特网接入能力的移动数字广播接收机的间接返回信道的方法 具有内部互联网访问功能的设备，以及使用具有内部因特网接入能力的外部因特网设备来确保间接返回信道的移动数字广播接收机。

公开(公告)号：US20130148458A1

公开(公告)日：2013-06-13

申请号：US13489562

申请日：2012-06-06

申请人： Sang Il PARK

发明人： Sang Il PARK

IPC分类号： G11C8/08 ,  H03K3/00

CPC分类号： G11C8/08 ,  H03K3/356104

摘要： A buffer circuit includes a pull-up element configured to pull-up drive a first node through which an output signal is outputted, in response to an input signal; a first voltage control element configured to reduce a voltage of the first node and set a voltage of a second node in a standby mode; and a pull-down element configured to pull-down drive the second node in response to the input signal.

摘要翻译： 缓冲电路包括：上拉元件，其被配置为上拉驱动响应于输入信号而输出输出信号的第一节点; 第一电压控制元件，被配置为降低所述第一节点的电压并将待机模式中的第二节点的电压设定; 以及下拉元件，其被配置为响应于所述输入信号下拉驱动所述第二节点。

公开(公告)号：US20110158022A1

公开(公告)日：2011-06-30

申请号：US12826918

申请日：2010-06-30

申请人： Duck Hwa HONG ,  Sang Il PARK

发明人： Duck Hwa HONG ,  Sang Il PARK

IPC分类号： G11C7/02

CPC分类号： G11C11/4091 ,  G11C7/02 ,  G11C7/06 ,  G11C7/08

摘要： A semiconductor memory device having a reduced noise interference is presented. The semiconductor memory device includes a first switch and a second switch. The first switch is disposed in a sub hole region or an edge region and is configured to be turned on in response to a first pre-control signal, which is enabled before a time point at which a sense amplifier array begins to operate, and to apply an external voltage to a first voltage line through which a bias voltage is supplied to the sense amplifier array. The second switch is configured to be turned on in response to a first control signal, which is enabled in a sense amplifier overdriving period, and to apply the external voltage to the first voltage line.

摘要翻译： 提出了具有降低的噪声干扰的半导体存储器件。 半导体存储器件包括第一开关和第二开关。 第一开关设置在子孔区域或边缘区域中，并且被配置为响应于在读出放大器阵列开始运行的时间点之前被使能的第一预控制信号而导通，以及 将外部电压施加到向读出放大器阵列提供偏置电压的第一电压线。 第二开关被配置为响应于在感测放大器过驱动周期中被使能的第一控制信号而导通，并且将外部电压施加到第一电压线。