公开(公告)号：US07217625B2

公开(公告)日：2007-05-15

申请号：US10753447

申请日：2004-01-09

申请人： Sang-Jin Lee ,  Kyung-Soo Kim ,  Chang-Bong Oh ,  Hee-Sung Kang

发明人： Sang-Jin Lee ,  Kyung-Soo Kim ,  Chang-Bong Oh ,  Hee-Sung Kang

IPC分类号： H01L21/336

CPC分类号： H01L29/6653 ,  H01L21/2652 ,  H01L21/26586 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of fabricating a semiconductor device forms a shallow source/drain region after a deep source/drain region. First, a gate insulating layer including a gate pattern and a gate electrode are formed on a semiconductor substrate. A buffer insulating layer, a first insulating layer, and a second insulating layer are then sequentially formed on the entire surface of the gate pattern and the semiconductor substrate. A first spacer is formed on the first insulating layer at both sidewalls of the gate pattern by etching the second insulating layer. A deep source/drain region is then formed on the semiconductor substrate as aligned by the first spacer. The first spacer is removed. Next, an offset spacer is formed at both sidewalls of the gate pattern by etching the first insulating layer. Finally, a shallow source/drain region is formed on the semiconductor substrate adjacent to the deep source/drain region as aligned by the offset spacer.

摘要翻译： 半导体器件的制造方法在深源极/漏极区域之后形成浅的源极/漏极区域。 首先，在半导体基板上形成包括栅极图案和栅电极的栅极绝缘层。 然后在栅极图案和半导体衬底的整个表面上依次形成缓冲绝缘层，第一绝缘层和第二绝缘层。 通过蚀刻第二绝缘层，在栅极图案的两个侧壁的第一绝缘层上形成第一间隔物。 然后在第一间隔物对准的半导体衬底上形成深源/漏区。 第一个垫片被去除。 接下来，通过蚀刻第一绝缘层在栅极图案的两个侧壁处形成偏移间隔物。 最后，在与偏移间隔物对齐的深源/漏区附近的半导体衬底上形成浅源极/漏极区。

公开(公告)号：US06855641B2

公开(公告)日：2005-02-15

申请号：US10421292

申请日：2003-04-23

申请人： Hyuk-Ju Ryu ,  Young-Wug Kim ,  Chang-Bong Oh ,  Hee-Sung Kang

发明人： Hyuk-Ju Ryu ,  Young-Wug Kim ,  Chang-Bong Oh ,  Hee-Sung Kang

IPC分类号： H01L21/28 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L21/31

CPC分类号： H01L27/092 ,  H01L21/823842

摘要： In a CMOS semiconductor device using a silicon germanium gate and a method of fabricating the same, a gate insulating layer, a conductive electrode layer that is a seed layer, a silicon germanium electrode layer, and an amorphous conductive electrode layer are sequentially formed on a semiconductor substrate. A photolithographic process is then carried out to remove the silicon germanium electrode layer in the NMOS region, so that the silicon germanium layer is formed only in the PMOS region and is not formed in the NMOS region.

公开(公告)号：US07348636B2

公开(公告)日：2008-03-25

申请号：US11030245

申请日：2005-01-06

申请人： Hyuk-Ju Ryu ,  Young-Wug Kim ,  Chang-Bong Oh ,  Hee-Sung Kang

发明人： Hyuk-Ju Ryu ,  Young-Wug Kim ,  Chang-Bong Oh ,  Hee-Sung Kang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L27/092 ,  H01L21/823842

摘要： In a CMOS semiconductor device using a silicon germanium gate and a method of fabricating the same, a gate insulating layer, a conductive electrode layer that is a seed layer, a silicon germanium electrode layer, and an amorphous conductive electrode layer are sequentially formed on a semiconductor substrate. A photolithographic process is then carried out to remove the silicon germanium electrode layer in the NMOS region, so that the silicon germanium layer is formed only in the PMOS region and is not formed in the NMOS region.

摘要翻译： 在使用硅锗栅极的CMOS半导体器件及其制造方法中，栅极绝缘层，作为晶种层的导电电极层，硅锗电极层和非晶导电电极层依次形成在 半导体衬底。 然后进行光刻工艺以除去NMOS区域中的硅锗电极层，使得硅锗层仅形成在PMOS区域中，并且不形成在NMOS区域中。

公开(公告)号：US20050116297A1

公开(公告)日：2005-06-02

申请号：US11030245

申请日：2005-01-06

申请人： Hyuk-Ju Ryu ,  Young-Wug Kim ,  Chang-Bong Oh ,  Hee-Sung Kang

发明人： Hyuk-Ju Ryu ,  Young-Wug Kim ,  Chang-Bong Oh ,  Hee-Sung Kang

IPC分类号： H01L21/28 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L21/336 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119

CPC分类号： H01L27/092 ,  H01L21/823842

摘要： In a CMOS semiconductor device using a silicon germanium gate and a method of fabricating the same, a gate insulating layer, a conductive electrode layer that is a seed layer, a silicon germanium electrode layer, and an amorphous conductive electrode layer are sequentially formed on a semiconductor substrate. A photolithographic process is then carried out to remove the silicon germanium electrode layer in the NMOS region, so that the silicon germanium layer is formed only in the PMOS region and is not formed in the NMOS region.

摘要翻译： 在使用硅锗栅极的CMOS半导体器件及其制造方法中，栅极绝缘层，作为晶种层的导电电极层，硅锗电极层和非晶导电电极层依次形成在 半导体衬底。 然后进行光刻工艺以除去NMOS区域中的硅锗电极层，使得硅锗层仅形成在PMOS区域中，并且不形成在NMOS区域中。

公开(公告)号：US20110272736A1

公开(公告)日：2011-11-10

申请号：US13102860

申请日：2011-05-06

申请人： JONGHO LEE ,  Chang-Bong Oh ,  Ho Lee ,  Myungsun Kim

发明人： JONGHO LEE ,  Chang-Bong Oh ,  Ho Lee ,  Myungsun Kim

IPC分类号： H01L29/165

CPC分类号： H01L21/823807 ,  H01L21/28238 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517

摘要： A semiconductor device includes a substrate including a first region and a second region each having an n-type region and a p-type region, wherein the n-type region in the first region includes a silicon channel, the p-type region in the first region includes a silicon germanium channel, and the n-type region and the p-type region in the second region respectively include a silicon channel. A first gate insulating pattern formed of a thermal oxide layer is disposed on the substrate of the n-type and p-type regions in the second region.

摘要翻译： 半导体器件包括：衬底，包括第一区域和第二区域，每个区域具有n型区域和p型区域，其中第一区域中的n型区域包括硅沟道， 第一区域包括硅锗沟道，并且第二区域中的n型区域和p型区域分别包括硅沟道。 在第二区域中的n型和p型区域的基板上设置由热氧化物层形成的第一栅极绝缘图案。

公开(公告)号：US20080054405A1

公开(公告)日：2008-03-06

申请号：US11825181

申请日：2007-07-05

申请人： Xiao Quan Wang ,  Chang-Bong Oh ,  Seung-Hwan Lee

发明人： Xiao Quan Wang ,  Chang-Bong Oh ,  Seung-Hwan Lee

IPC分类号： H01L29/06 ,  H01L21/02

CPC分类号： H01L27/0802 ,  H01L28/20

摘要： A semiconductor device may include a resistance pattern including a resistance material on a substrate. The resistance pattern may include first and second spaced apart base elements, a bridge element, and first, second, third, and fourth extension elements. The first and second base elements may be substantially parallel, and the bridge element may be connected between respective center portions of the first and second spaced apart base elements. The first and second extension elements may be connected to opposite ends of the first base element and may extend toward the second base element, and the third and fourth extension elements may be connected to opposite ends of the second base element and may extend toward the first base element. Related methods are also discussed.

摘要翻译： 半导体器件可以包括在基板上包括电阻材料的电阻图案。 电阻图案可以包括第一和第二间隔开的基本元件，桥接元件以及第一，第二，第三和第四延伸元件。 第一和第二基座元件可以是基本上平行的，并且桥接元件可以连接在第一和第二间隔开的基本元件的相应中心部分之间。 第一和第二延伸元件可以连接到第一基座元件的相对端并且可以朝向第二基座元件延伸，并且第三和第四延伸元件可以连接到第二基座元件的相对端并且可以朝着第一基座元件 基本元素 还讨论了相关方法。

公开(公告)号：US08482077B2

公开(公告)日：2013-07-09

申请号：US13102860

申请日：2011-05-06

申请人： Jongho Lee ,  Chang-Bong Oh ,  Ho Lee ,  Myungsun Kim

发明人： Jongho Lee ,  Chang-Bong Oh ,  Ho Lee ,  Myungsun Kim

IPC分类号： H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/28238 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/517

摘要： A semiconductor device includes a substrate including a first region and a second region each having an n-type region and a p-type region, wherein the n-type region in the first region includes a silicon channel, the p-type region in the first region includes a silicon germanium channel, and the n-type region and the p-type region in the second region respectively include a silicon channel. A first gate insulating pattern formed of a thermal oxide layer is disposed on the substrate of the n-type and p-type regions in the second region.

摘要翻译： 半导体器件包括：衬底，包括第一区域和第二区域，每个区域具有n型区域和p型区域，其中第一区域中的n型区域包括硅沟道， 第一区域包括硅锗沟道，并且第二区域中的n型区域和p型区域分别包括硅沟道。 在第二区域中的n型和p型区域的基板上设置由热氧化物层形成的第一栅极绝缘图案。

公开(公告)号：US07838966B2

公开(公告)日：2010-11-23

申请号：US11825181

申请日：2007-07-05

申请人： Xiao Quan Wang ,  Chang-Bong Oh ,  Seung-Hwan Lee

发明人： Xiao Quan Wang ,  Chang-Bong Oh ,  Seung-Hwan Lee

IPC分类号： H01L23/62

CPC分类号： H01L27/0802 ,  H01L28/20

摘要： A semiconductor device may include a resistance pattern including a resistance material on a substrate. The resistance pattern may include first and second spaced apart base elements, a bridge element, and first, second, third, and fourth extension elements. The first and second base elements may be substantially parallel, and the bridge element may be connected between respective center portions of the first and second spaced apart base elements. The first and second extension elements may be connected to opposite ends of the first base element and may extend toward the second base element, and the third and fourth extension elements may be connected to opposite ends of the second base element and may extend toward the first base element. Related methods are also discussed.

摘要翻译： 半导体器件可以包括在基板上包括电阻材料的电阻图案。 电阻图案可以包括第一和第二间隔开的基本元件，桥接元件以及第一，第二，第三和第四延伸元件。 第一和第二基座元件可以是基本上平行的，并且桥接元件可以连接在第一和第二间隔开的基本元件的相应中心部分之间。 第一和第二延伸元件可以连接到第一基座元件的相对端并且可以朝向第二基座元件延伸，并且第三和第四延伸元件可以连接到第二基座元件的相对端并且可以朝着第一基座元件 基本元素 还讨论了相关方法。