公开(公告)号：US10043583B2

公开(公告)日：2018-08-07

申请号：US15447357

申请日：2017-03-02

申请人： Sang-wan Nam ,  Dae-seok Byeon ,  Chi-weon Yoon

发明人： Sang-wan Nam ,  Dae-seok Byeon ,  Chi-weon Yoon

IPC分类号： G11C11/34 ,  G11C16/34 ,  G11C16/04 ,  G11C16/28 ,  G11C16/10 ,  G11C16/16

摘要： Provided are a nonvolatile memory device and a method of performing a sensing operation on the nonvolatile memory device. The nonvolatile memory device includes a control logic coupled to a memory cell array including strings. The control logic is configured to control a first weak-on voltage applied to an unselected string selection line and a second weak-on voltage applied to an unselected ground selection line during a setup interval of the sensing operation for sensing data from a selected string. The unselected string selection line and ground selection line are connected to a string selection transistor and a ground selection transistor, respectively, of a same unselected string. The selected string and the unselected string are connected to a same bit line. The first weak-on voltage and second weak-on voltage are respectively less than a threshold voltage of the string selection transistor and the ground selection transistor in the unselected string.

公开(公告)号：US09842659B2

公开(公告)日：2017-12-12

申请号：US14616281

申请日：2015-02-06

申请人： Sang-wan Nam ,  Byung-gil Jeon ,  Dae-seok Byeon

发明人： Sang-wan Nam ,  Byung-gil Jeon ,  Dae-seok Byeon

IPC分类号： G11C11/34 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50

CPC分类号： G11C29/025 ,  G11C2029/1202 ,  G11C2029/5006

摘要： Provided are a non-volatile memory device, a memory system, and a method of operating the non-volatile memory device. The method includes: performing a user operation according to at least one mode selected from among a writing mode, a reading mode, and an erasing mode with respect to a memory cell array; setting up voltages of a plurality of word lines; floating at least one word line from among the plurality of word lines, the voltages of which are set up, according to the at least one selected mode; and detecting whether the at least one word line has a progressive defect, according to a result of detecting a voltage level of the at least one floated word line.

公开(公告)号：US09721664B2

公开(公告)日：2017-08-01

申请号：US14605433

申请日：2015-01-26

申请人： Sang-wan Nam ,  Kyung-min Kang

发明人： Sang-wan Nam ,  Kyung-min Kang

IPC分类号： G11C11/34 ,  G11C16/10 ,  G11C16/04 ,  G11C7/14

CPC分类号： G11C16/10 ,  G11C7/14 ,  G11C16/0483

摘要： A method of operating a memory device including a first memory block having a plurality cell strings is provided. Each of the plurality of cell strings includes a string selection transistor connected in series to a first dummy cell, a plurality of normal cells, a second dummy cell and a ground selection transistor. The method includes programming the first dummy cell, and programming the normal cells in at least one of the cell strings after the programming the first dummy cell. The normal cells are selected based on a first program command inputted to the memory device. The programming the first dummy cell is performed at least twice before the normal cells are programmed. A number of times of programming the first dummy cell is different according to a level of a voltage applied to the first dummy cell and a level of a voltage applied to the normal cells.

公开(公告)号：US20070171723A1

公开(公告)日：2007-07-26

申请号：US11606029

申请日：2006-11-30

申请人： Sang-wan Nam ,  Dae-han Kim

发明人： Sang-wan Nam ,  Dae-han Kim

IPC分类号： G11C16/06

CPC分类号： G11C16/26

摘要： A NOR flash memory is disclosed including a memory cell, sense amplifier output driver, and control circuit. A sense period for a sense operation performed by the sense amplifier is made synchronous with a clock signal so as to avoid power supply or ground signal noise generated by operation of the output driver.

摘要翻译： 公开了一种NOR闪存，其包括存储单元，读出放大器输出驱动器和控制电路。 由读出放大器执行的感测操作的感测周期与时钟信号同步，以避免由输出驱动器的操作产生的电源或接地信号噪声。

公开(公告)号：US20130028027A1

公开(公告)日：2013-01-31

申请号：US13526896

申请日：2012-06-19

申请人： Jung-soo Kim ,  Sang-wan Nam

发明人： Jung-soo Kim ,  Sang-wan Nam

IPC分类号： G11C16/06

CPC分类号： G11C16/344 ,  G11C16/0483 ,  G11C16/06

摘要： A 3D semiconductor memory device including a plurality of memory cell strings, includes a substrate and a channel that extends from the substrate. Memory cells may be disposed in layers in which the diameter of the channel varies. A programming verification operation may be carried out in a sequence whereby memory cells more likely to fail in programming are verified before attempting to verify memory cells that are less likely to fail programming. In an exemplary embodiment, the verification operation is performed on a memory cell disposed in a layer associated with a larger-diameter channel before performing the verification on a memory cell disposed in a layer associated with a smaller-diameter channel. In an exemplary embodiment, if a verification process detects a programming failure, the verification of subsequent memory cells is cancelled.

摘要翻译： 包括多个存储单元串的3D半导体存储器件包括衬底和从衬底延伸的沟道。 存储单元可以设置在通道直径变化的层中。 编程验证操作可以按照顺序执行，由此在尝试验证不太可能编程失败的存储器单元之前，验证编程中更容易失败的存储器单元。 在示例性实施例中，对设置在与较大直径信道相关联的层中的存储器单元执行验证操作，然后对与设置在与较小直径信道相关联的层中的存储单元执行验证。 在示例性实施例中，如果验证过程检测到编程失败，则后续存储器单元的验证被取消。

公开(公告)号：US08848451B2

公开(公告)日：2014-09-30

申请号：US13526896

申请日：2012-06-19

申请人： Jung-soo Kim ,  Sang-wan Nam

发明人： Jung-soo Kim ,  Sang-wan Nam

IPC分类号： G11C16/04 ,  G11C16/34 ,  G11C16/06

CPC分类号： G11C16/344 ,  G11C16/0483 ,  G11C16/06

摘要： A 3D semiconductor memory device including a plurality of memory cell strings, includes a substrate and a channel that extends from the substrate. Memory cells may be disposed in layers in which the diameter of the channel varies. A programming verification operation may be carried out in a sequence whereby memory cells more likely to fail in programming are verified before attempting to verify memory cells that are less likely to fail programming. In an exemplary embodiment, the verification operation is performed on a memory cell disposed in a layer associated with a larger-diameter channel before performing the verification on a memory cell disposed in a layer associated with a smaller-diameter channel. In an exemplary embodiment, if a verification process detects a programming failure, the verification of subsequent memory cells is cancelled.

摘要翻译： 包括多个存储单元串的3D半导体存储器件包括衬底和从衬底延伸的沟道。 存储单元可以设置在通道直径变化的层中。 编程验证操作可以按照顺序执行，由此在尝试验证不太可能编程失败的存储器单元之前，验证编程中更容易失败的存储器单元。 在示例性实施例中，对设置在与较大直径信道相关联的层中的存储器单元执行验证操作，然后对与设置在与较小直径信道相关联的层中的存储单元执行验证。 在示例性实施例中，如果验证过程检测到编程失败，则后续存储器单元的验证被取消。

公开(公告)号：US07616497B2

公开(公告)日：2009-11-10

申请号：US11606029

申请日：2006-11-30

申请人： Sang-wan Nam ,  Dae-han Kim

发明人： Sang-wan Nam ,  Dae-han Kim

IPC分类号： G11C16/06 ,  G11C7/02

CPC分类号： G11C16/26

摘要： A NOR flash memory is disclosed including a memory cell, sense amplifier output driver, and control circuit. A sense period for a sense operation performed by the sense amplifier is made synchronous with a clock signal so as to avoid power supply or ground signal noise generated by operation of the output driver.

摘要翻译： 公开了一种NOR闪存，其包括存储单元，读出放大器输出驱动器和控制电路。 由读出放大器执行的感测操作的感测周期与时钟信号同步，以避免由输出驱动器的操作产生的电源或接地信号噪声。

公开(公告)号：US07495961B2

公开(公告)日：2009-02-24

申请号：US11563746

申请日：2006-11-28

申请人： Ji-ho Cho ,  Sang-wan Nam

发明人： Ji-ho Cho ,  Sang-wan Nam

IPC分类号： G11C11/34

CPC分类号： G11C16/24 ,  G11C7/067 ,  G11C7/12 ,  G11C16/26

摘要： A sense amplifier of a flash memory device maintains a bit line precharge level before a memory cell is sensed. The sense amplifier maintains the voltage of a bias signal sufficiently high using a second precharging circuit in a precharging operation to stably maintain the bit line precharge level set by a first precharging circuit. Accordingly, the sense amplifier can correctly sense an OFF cell using the stabilized bit line precharge voltage. Related methods and memory devices are also disclosed.

摘要翻译： 闪速存储器件的读出放大器在感测存储器单元之前保持位线预充电电平。 读出放大器在预充电操作中使用第二预充电电路来保持偏置信号的电压足够高以稳定地维持由第一预充电电路设置的位线预充电电平。 因此，读出放大器可以使用稳定的位线预充电电压来正确地感测OFF单元。 还公开了相关方法和存储器件。