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    Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer
    1.
    发明申请
    Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer 有权
    具有在退火的高k栅介质层上形成的金属栅电极的半导体器件

    公开(公告)号：US20070045753A1

    公开(公告)日：2007-03-01

    申请号：US11216596

    申请日：2005-08-30

    申请人： Sangwoo Pae ,  Jose Maiz ,  Justin Brask ,  Gilbert Dewey ,  Jack Kavalieros ,  Robert Chau ,  Suman Datta

    发明人： Sangwoo Pae ,  Jose Maiz ,  Justin Brask ,  Gilbert Dewey ,  Jack Kavalieros ,  Robert Chau ,  Suman Datta

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/28185 ,  H01L21/28088 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583

    摘要： A method of forming a transistor gate stack having an annealed gate dielectric layer begins by providing a substrate that includes a first and second spacer separated by a trench. A conformal high-k gate dielectric layer is deposited on the substrate and within the trench with a thickness that ranges from 3 Å to 60 Å. Next, a capping layer is deposited on the high-k gate dielectric layer that substantially fills the trench and covers the high-k gate dielectric layer. The high-k gate dielectric layer is then annealed at a temperature that is greater than or equal to 600° C. The capping layer is removed to expose an annealed high-k gate dielectric layer. A metal layer is then deposited on the annealed high-k gate dielectric layer. A CMP process may be used to remove excess material and complete formation of the transistor gate stack.

    摘要翻译： 形成具有退火栅极电介质层的晶体管栅极堆叠的方法开始于提供包括由沟槽分隔开的第一和第二间隔物的衬底。 保形高k栅极电介质层沉积在衬底上并且在沟槽内沉积，厚度范围为3埃至60埃。 接下来，在高k栅极电介质层上沉积盖层，其基本上填充沟槽并覆盖高k栅极电介质层。 然后将高k栅极电介质层在大于或等于600℃的温度下退火。去除覆盖层以暴露退火的高k栅极电介质层。 然后在退火的高k栅极电介质层上沉积金属层。 可以使用CMP工艺来去除多余的材料并完成晶体管栅叠层的形成。

    Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer
    2.
    发明授权
    Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer 有权
    具有在退火的高k栅介质层上形成的金属栅电极的半导体器件

    公开(公告)号：US07531404B2

    公开(公告)日：2009-05-12

    申请号：US11216596

    申请日：2005-08-30

    申请人： Sangwoo Pae ,  Jose Maiz ,  Justin Brask ,  Gilbert Dewey ,  Jack Kavalieros ,  Robert Chau ,  Suman Datta

    发明人： Sangwoo Pae ,  Jose Maiz ,  Justin Brask ,  Gilbert Dewey ,  Jack Kavalieros ,  Robert Chau ,  Suman Datta

    IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/3205

    CPC分类号： H01L21/28185 ,  H01L21/28088 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583

    摘要： A method of forming a transistor gate stack having an annealed gate dielectric layer begins by providing a substrate that includes a first and second spacer separated by a trench. A conformal high-k gate dielectric layer is deposited on the substrate and within the trench with a thickness that ranges from 3 Å to 60 Å. Next, a capping layer is deposited on the high-k gate dielectric layer that substantially fills the trench and covers the high-k gate dielectric layer. The high-k gate dielectric layer is then annealed at a temperature that is greater than or equal to 600° C. The capping layer is removed to expose an annealed high-k gate dielectric layer. A metal layer is then deposited on the annealed high-k gate dielectric layer. A CMP process may be used to remove excess material and complete formation of the transistor gate stack.

    摘要翻译： 形成具有退火栅极电介质层的晶体管栅极堆叠的方法开始于提供包括由沟槽分隔开的第一和第二间隔物的衬底。 保形高k栅极电介质层沉积在衬底上并且在沟槽内沉积，厚度范围为3埃至60埃。 接下来，在高k栅极电介质层上沉积盖层，其基本上填充沟槽并覆盖高k栅极电介质层。 然后将高k栅极电介质层在大于或等于600℃的温度下退火。去除覆盖层以暴露退火的高k栅极电介质层。 然后在退火的高k栅极电介质层上沉积金属层。 可以使用CMP工艺来去除多余的材料并完成晶体管栅叠层的形成。