公开(公告)号：US20060166447A1

公开(公告)日：2006-07-27

申请号：US11390892

申请日：2006-03-27

申请人： Mark Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Adrian Sherrill ,  Markus Kuhn ,  Robert Chau

发明人： Mark Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Adrian Sherrill ,  Markus Kuhn ,  Robert Chau

IPC分类号： H01L21/336

CPC分类号： H01L21/0214 ,  H01L21/02142 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/3144 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/517 ,  H01L29/518

摘要： A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.

公开(公告)号：US20060051882A1

公开(公告)日：2006-03-09

申请号：US11210220

申请日：2005-08-22

申请人： Mark Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Adrian Sherrill ,  Markus Kuhn ,  Robert Chau

发明人： Mark Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Adrian Sherrill ,  Markus Kuhn ,  Robert Chau

IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L21/20

CPC分类号： H01L21/0214 ,  H01L21/02142 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/3144 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/517 ,  H01L29/518

摘要： A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.

公开(公告)号：US20060051880A1

公开(公告)日：2006-03-09

申请号：US10935784

申请日：2004-09-07

申请人： Mark Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Adrian Sherrill ,  Markus Kuhn ,  Robert Chau

发明人： Mark Doczy ,  Gilbert Dewey ,  Suman Datta ,  Sangwoo Pae ,  Justin Brask ,  Jack Kavalieros ,  Matthew Metz ,  Adrian Sherrill ,  Markus Kuhn ,  Robert Chau

IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L21/20

CPC分类号： H01L21/0214 ,  H01L21/02142 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/3144 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/517 ,  H01L29/518

摘要： A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.

公开(公告)号：US20060121678A1

公开(公告)日：2006-06-08

申请号：US11006218

申请日：2004-12-07

申请人： Justin Brask ,  Sangwoo Pae ,  Jack Kavalieros ,  Matthew Metz ,  Mark Doczy ,  Suman Datta ,  Robert Chau ,  Jose Maiz

发明人： Justin Brask ,  Sangwoo Pae ,  Jack Kavalieros ,  Matthew Metz ,  Mark Doczy ,  Suman Datta ,  Robert Chau ,  Jose Maiz

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/28079 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method for making a semiconductor device is described. That method comprises adding nitrogen to a silicon dioxide layer to form a nitrided silicon dioxide layer on a substrate. After forming a sacrificial layer on the nitrided silicon dioxide layer, the sacrificial layer is removed to generate a trench. A high-k gate dielectric layer is formed on the nitrided silicon dioxide layer within the trench, and a metal gate electrode is formed on the high-k gate dielectric layer.

摘要翻译： 描述制造半导体器件的方法。 该方法包括向二氧化硅层中加入氮以在基底上形成氮化二氧化硅层。 在氮化二氧化硅层上形成牺牲层之后，除去牺牲层以产生沟槽。 在沟槽内的氮化二氧化硅层上形成高k栅介质层，在高k栅介质层上形成金属栅电极。

公开(公告)号：US20080087985A1

公开(公告)日：2008-04-17

申请号：US11998236

申请日：2007-11-29

申请人： Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Uday Shah ,  Gilbert Dewey ,  Robert Chau

发明人： Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Uday Shah ,  Gilbert Dewey ,  Robert Chau

IPC分类号： H01L23/58

CPC分类号： H01L21/0228 ,  H01L21/02052 ,  H01L21/02175 ,  H01L21/28167 ,  H01L21/3141 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

摘要： A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations prior to deposition.

摘要翻译： 可以在平滑的硅衬底上形成缓冲层和高k金属氧化物电介质。 衬底平滑度可能降低高k金属氧化物栅极电介质的柱生长。 在沉积之前，衬底的表面可能被羟基终止物饱和。

公开(公告)号：US20060001071A1

公开(公告)日：2006-01-05

申请号：US10882734

申请日：2004-06-30

申请人： Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Uday Shah ,  Gilbert Dewey ,  Robert Chau

发明人： Justin Brask ,  Jack Kavalieros ,  Mark Doczy ,  Matthew Metz ,  Suman Datta ,  Uday Shah ,  Gilbert Dewey ,  Robert Chau

IPC分类号： H01L21/8238 ,  H01L27/108

CPC分类号： H01L21/0228 ,  H01L21/02052 ,  H01L21/02175 ,  H01L21/28167 ,  H01L21/3141 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

摘要： A buffer layer and a high-k metal oxide dielectric may be formed over a smooth silicon substrate. The substrate smoothness may reduce column growth of the high-k metal oxide gate dielectric. The surface of the substrate may be saturated with hydroxyl terminations prior to deposition.

公开(公告)号：US20060292776A1

公开(公告)日：2006-12-28

申请号：US11167647

申请日：2005-06-27

申请人： Been-Yih Jin ,  Robert Chau ,  Suman Datta ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Matthew Metz ,  Markus Kuhn ,  Marko Radosavlievic ,  M. Shaheed ,  Patrick Keys

发明人： Been-Yih Jin ,  Robert Chau ,  Suman Datta ,  Brian Doyle ,  Jack Kavalieros ,  Justin Brask ,  Mark Doczy ,  Matthew Metz ,  Markus Kuhn ,  Marko Radosavlievic ,  M. Shaheed ,  Patrick Keys

IPC分类号： H01L21/8234 ,  H01L21/20 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/7848

摘要： An NMOS transistor may be formed with a biaxially strained silicon upper layer having a thickness of greater than 500 Angstroms. The resulting NMOS transistor may have good performance and may exhibit reduced self-heating. A PMOS transistor may be formed with both a biaxially and uniaxially strained silicon germanium layer. A source substrate bias applied to both NMOS and PMOS transistors can enhance their performance.

摘要翻译： NMOS晶体管可以形成为具有大于500埃的厚度的双轴应变硅上层。 所得的NMOS晶体管可以具有良好的性能并且可以表现出减少的自热。 PMOS晶体管可以形成为双轴和单轴应变的硅锗层。 施加到NMOS和PMOS晶体管的源极衬底偏置可以提高其性能。

公开(公告)号：US20060060930A1

公开(公告)日：2006-03-23

申请号：US10943693

申请日：2004-09-17

申请人： Matthew Metz ,  Clifford Boyd ,  Markus Kuhn ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

发明人： Matthew Metz ,  Clifford Boyd ,  Markus Kuhn ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/517 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/7833

摘要： Gate dielectrics formed of silicates of hafnium or zirconium dioxide may be formed by atomic layer deposition. The precursors for the atomic layer deposition may include an oxidant, a silicate precursor, and a zirconium or hafnium precursor.

摘要翻译： 可以通过原子层沉积形成由铪或二氧化锆的硅酸盐形成的栅极电介质。 原子层沉积的前体可以包括氧化剂，硅酸盐前体和锆或铪前体。

公开(公告)号：US20060045968A1

公开(公告)日：2006-03-02

申请号：US10925573

申请日：2004-08-25

申请人： Matthew Metz ,  Mark Brazier ,  Timothy Glassman ,  Christopher Thomas ,  Lawrence Foley ,  Christopher Parker ,  Ying Zhou ,  Markus Kuhn ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

发明人： Matthew Metz ,  Mark Brazier ,  Timothy Glassman ,  Christopher Thomas ,  Lawrence Foley ,  Christopher Parker ,  Ying Zhou ,  Markus Kuhn ,  Suman Datta ,  Jack Kavalieros ,  Mark Doczy ,  Justin Brask ,  Robert Chau

IPC分类号： C23C16/00

CPC分类号： C23C16/45527

摘要： Increasing the number of successive pulses of oxidant before applying pulses of metal precursor may improve the quality of the resulting metal or rare earth oxide films. These metal or rare earth oxide films may be utilized for high dielectric constant gate dielectrics. In addition, pulsing the oxidant during the pre-stabilization period may be advantageous. Also, using more pulses of oxidant than the pulses of precursor may reduce chlorine concentration in the resulting films.

摘要翻译： 在施加金属前体的脉冲之前增加氧化剂的连续脉冲数可以提高所得金属或稀土氧化物膜的质量。 这些金属或稀土氧化物膜可用于高介电常数栅极电介质。 此外，在预稳定化期间脉冲氧化剂可能是有利的。 此外，使用比前体脉冲更多的氧化剂脉冲可以降低所得膜中的氯浓度。

公开(公告)号：US20070045753A1

公开(公告)日：2007-03-01

申请号：US11216596

申请日：2005-08-30

申请人： Sangwoo Pae ,  Jose Maiz ,  Justin Brask ,  Gilbert Dewey ,  Jack Kavalieros ,  Robert Chau ,  Suman Datta

发明人： Sangwoo Pae ,  Jose Maiz ,  Justin Brask ,  Gilbert Dewey ,  Jack Kavalieros ,  Robert Chau ,  Suman Datta

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/28185 ,  H01L21/28088 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583

摘要： A method of forming a transistor gate stack having an annealed gate dielectric layer begins by providing a substrate that includes a first and second spacer separated by a trench. A conformal high-k gate dielectric layer is deposited on the substrate and within the trench with a thickness that ranges from 3 Å to 60 Å. Next, a capping layer is deposited on the high-k gate dielectric layer that substantially fills the trench and covers the high-k gate dielectric layer. The high-k gate dielectric layer is then annealed at a temperature that is greater than or equal to 600° C. The capping layer is removed to expose an annealed high-k gate dielectric layer. A metal layer is then deposited on the annealed high-k gate dielectric layer. A CMP process may be used to remove excess material and complete formation of the transistor gate stack.

摘要翻译： 形成具有退火栅极电介质层的晶体管栅极堆叠的方法开始于提供包括由沟槽分隔开的第一和第二间隔物的衬底。 保形高k栅极电介质层沉积在衬底上并且在沟槽内沉积，厚度范围为3埃至60埃。 接下来，在高k栅极电介质层上沉积盖层，其基本上填充沟槽并覆盖高k栅极电介质层。 然后将高k栅极电介质层在大于或等于600℃的温度下退火。去除覆盖层以暴露退火的高k栅极电介质层。 然后在退火的高k栅极电介质层上沉积金属层。 可以使用CMP工艺来去除多余的材料并完成晶体管栅叠层的形成。