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    Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer
    1.
    发明申请
    Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer 有权
    具有在退火的高k栅介质层上形成的金属栅电极的半导体器件

    公开(公告)号：US20070045753A1

    公开(公告)日：2007-03-01

    申请号：US11216596

    申请日：2005-08-30

    申请人： Sangwoo Pae ,  Jose Maiz ,  Justin Brask ,  Gilbert Dewey ,  Jack Kavalieros ,  Robert Chau ,  Suman Datta

    发明人： Sangwoo Pae ,  Jose Maiz ,  Justin Brask ,  Gilbert Dewey ,  Jack Kavalieros ,  Robert Chau ,  Suman Datta

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/28185 ,  H01L21/28088 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583

    摘要： A method of forming a transistor gate stack having an annealed gate dielectric layer begins by providing a substrate that includes a first and second spacer separated by a trench. A conformal high-k gate dielectric layer is deposited on the substrate and within the trench with a thickness that ranges from 3 Å to 60 Å. Next, a capping layer is deposited on the high-k gate dielectric layer that substantially fills the trench and covers the high-k gate dielectric layer. The high-k gate dielectric layer is then annealed at a temperature that is greater than or equal to 600° C. The capping layer is removed to expose an annealed high-k gate dielectric layer. A metal layer is then deposited on the annealed high-k gate dielectric layer. A CMP process may be used to remove excess material and complete formation of the transistor gate stack.

    摘要翻译： 形成具有退火栅极电介质层的晶体管栅极堆叠的方法开始于提供包括由沟槽分隔开的第一和第二间隔物的衬底。 保形高k栅极电介质层沉积在衬底上并且在沟槽内沉积，厚度范围为3埃至60埃。 接下来，在高k栅极电介质层上沉积盖层，其基本上填充沟槽并覆盖高k栅极电介质层。 然后将高k栅极电介质层在大于或等于600℃的温度下退火。去除覆盖层以暴露退火的高k栅极电介质层。 然后在退火的高k栅极电介质层上沉积金属层。 可以使用CMP工艺来去除多余的材料并完成晶体管栅叠层的形成。

    Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer
    2.
    发明授权
    Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer 有权
    具有在退火的高k栅介质层上形成的金属栅电极的半导体器件

    公开(公告)号：US07531404B2

    公开(公告)日：2009-05-12

    申请号：US11216596

    申请日：2005-08-30

    申请人： Sangwoo Pae ,  Jose Maiz ,  Justin Brask ,  Gilbert Dewey ,  Jack Kavalieros ,  Robert Chau ,  Suman Datta

    发明人： Sangwoo Pae ,  Jose Maiz ,  Justin Brask ,  Gilbert Dewey ,  Jack Kavalieros ,  Robert Chau ,  Suman Datta

    IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/3205

    CPC分类号： H01L21/28185 ,  H01L21/28088 ,  H01L29/495 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583

    摘要： A method of forming a transistor gate stack having an annealed gate dielectric layer begins by providing a substrate that includes a first and second spacer separated by a trench. A conformal high-k gate dielectric layer is deposited on the substrate and within the trench with a thickness that ranges from 3 Å to 60 Å. Next, a capping layer is deposited on the high-k gate dielectric layer that substantially fills the trench and covers the high-k gate dielectric layer. The high-k gate dielectric layer is then annealed at a temperature that is greater than or equal to 600° C. The capping layer is removed to expose an annealed high-k gate dielectric layer. A metal layer is then deposited on the annealed high-k gate dielectric layer. A CMP process may be used to remove excess material and complete formation of the transistor gate stack.

    摘要翻译： 形成具有退火栅极电介质层的晶体管栅极堆叠的方法开始于提供包括由沟槽分隔开的第一和第二间隔物的衬底。 保形高k栅极电介质层沉积在衬底上并且在沟槽内沉积，厚度范围为3埃至60埃。 接下来，在高k栅极电介质层上沉积盖层，其基本上填充沟槽并覆盖高k栅极电介质层。 然后将高k栅极电介质层在大于或等于600℃的温度下退火。去除覆盖层以暴露退火的高k栅极电介质层。 然后在退火的高k栅极电介质层上沉积金属层。 可以使用CMP工艺来去除多余的材料并完成晶体管栅叠层的形成。

    High quality silicon oxynitride transition layer for high-k/metal gate transistors
    10.
    发明申请
    High quality silicon oxynitride transition layer for high-k/metal gate transistors 审中-公开
    高k /金属栅晶体管的高品质氮氧化硅过渡层

    公开(公告)号：US20080242012A1

    公开(公告)日：2008-10-02

    申请号：US11729188

    申请日：2007-03-28

    申请人： Sangwoo Pae ,  Jose Maiz ,  Gilbert Dewey ,  Matthew V. Metz ,  Markus Kuhn ,  Mark Doczy ,  Jack Kavalieros

    发明人： Sangwoo Pae ,  Jose Maiz ,  Gilbert Dewey ,  Matthew V. Metz ,  Markus Kuhn ,  Mark Doczy ,  Jack Kavalieros

    IPC分类号： H01L21/8234 ,  H01L21/336

    CPC分类号： H01L29/517 ,  H01L21/28079 ,  H01L21/28194 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method for fabricating a high quality silicon oxynitride layer for a high-k/metal gate transistor comprises depositing a high-k dielectric layer on a substrate, depositing a barrier layer on the high-k dielectric layer, wherein the barrier layer includes at least one of nitrogen or oxygen, depositing a capping layer on the barrier layer, and annealing the substrate at a temperature that causes at least a portion of the nitrogen and/or oxygen in the barrier layer to diffuse to an interface between the high-k dielectric layer and the substrate. The diffused nitrogen or oxygen forms a high-quality silicon oxynitride layer at the interface. The high-k dielectric layer, the barrier layer, and the capping layer may then be etched to form a gate stack for use in a high-k/metal gate transistor. The capping layer may be replaced with a metal gate electrode using a replacement metal gate process.

    摘要翻译： 制造用于高k /金属栅极晶体管的高质量氮氧化硅层的方法包括在衬底上沉积高k电介质层，在高k电介质层上沉积阻挡层，其中阻挡层至少包括 氮气或氧气中的一种，在阻挡层上沉积覆盖层，并且在使阻挡层中的氮和/或氧的至少一部分扩散到高k电介质 层和基底。 扩散的氮或氧在界面处形成高质量的氮氧化硅层。 然后可以蚀刻高k电介质层，阻挡层和覆盖层以形成用于高k /金属栅极晶体管的栅极堆叠。 使用替代金属浇口工艺可以用金属栅电极代替覆盖层。