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公开(公告)号：US07659560B2
公开(公告)日：2010-02-09
申请号：US11716433
申请日：2007-03-08
申请人： Sanh D. Tang , Gordon A. Haller , Prashant Raghu , Ravi Iyer
发明人： Sanh D. Tang , Gordon A. Haller , Prashant Raghu , Ravi Iyer
IPC分类号： H01L21/8238
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66787
摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.
摘要翻译： 晶体管栅极形成方法包括在线路开口内形成金属层，并在金属层的开口内形成填充层。 填充层相对于金属层基本上可选择性地蚀刻。 晶体管结构包括线路开口，开口内的电介质层，开口内的电介质层上的金属层，以及开口内的金属层上的填充层。 如果填充层被金属层的增加的厚度代替，则金属层/填充层组合的内在特性小于否则会存在。 本发明至少应用于三维晶体管结构。
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公开(公告)号：US20110092062A1
公开(公告)日：2011-04-21
申请号：US12977969
申请日：2010-12-23
申请人： Sanh D. Tang , Gordon A. Haller , Prashant Raghu , Ravi Iyer
发明人： Sanh D. Tang , Gordon A. Haller , Prashant Raghu , Ravi Iyer
IPC分类号： H01L21/28
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66787
摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.
摘要翻译： 晶体管栅极形成方法包括在线路开口内形成金属层，并在金属层的开口内形成填充层。 填充层相对于金属层基本上可选择性地蚀刻。 晶体管结构包括线路开口，开口内的电介质层，开口内的电介质层上的金属层，以及开口内的金属层上的填充层。 如果填充层被金属层的增加的厚度代替，则金属层/填充层组合的内在特性小于否则会存在。 本发明至少应用于三维晶体管结构。
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公开(公告)号：US07867845B2
公开(公告)日：2011-01-11
申请号：US11219077
申请日：2005-09-01
申请人： Sanh D. Tang , Gordon A. Haller , Prashant Raghu , Ravi Iyer
发明人： Sanh D. Tang , Gordon A. Haller , Prashant Raghu , Ravi Iyer
IPC分类号： H01L29/76
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66787
摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.
摘要翻译： 晶体管栅极形成方法包括在线路开口内形成金属层，并在金属层的开口内形成填充层。 填充层相对于金属层基本上可选择性地蚀刻。 晶体管结构包括线路开口，开口内的电介质层，开口内的电介质层上的金属层，以及开口内的金属层上的填充层。 如果填充层被金属层的增加的厚度代替，则金属层/填充层组合的内在特性小于否则会存在。 本发明至少应用于三维晶体管结构。
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公开(公告)号：US08349687B2
公开(公告)日：2013-01-08
申请号：US12977969
申请日：2010-12-23
申请人： Sanh D. Tang , Gordon A. Haller , Prashant Raghu , Ravi Iyer
发明人： Sanh D. Tang , Gordon A. Haller , Prashant Raghu , Ravi Iyer
IPC分类号： H01L29/76
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66787
摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.
摘要翻译： 晶体管栅极形成方法包括在线路开口内形成金属层，并在金属层的开口内形成填充层。 填充层相对于金属层基本上可选择性地蚀刻。 晶体管结构包括线路开口，开口内的电介质层，开口内的电介质层上的金属层，以及开口内的金属层上的填充层。 如果填充层被金属层的增加的厚度代替，则金属层/填充层组合的内在特性小于否则会存在。 本发明至少应用于三维晶体管结构。
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公开(公告)号：US09076888B2
公开(公告)日：2015-07-07
申请号：US11614802
申请日：2006-12-21
申请人： Hasan Nejad , Thomas A. Figura , Gordon A. Haller , Ravi Iyer , John Mark Meldrim , Justin Harnish
发明人： Hasan Nejad , Thomas A. Figura , Gordon A. Haller , Ravi Iyer , John Mark Meldrim , Justin Harnish
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/8238 , H01L21/28 , H01L21/8234 , H01L27/108 , H01L29/49 , H01L29/66
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823418 , H01L21/823443 , H01L21/823814 , H01L27/10852 , H01L27/10876 , H01L27/10897 , H01L29/4975 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.
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6.发明申请Method Of Forming A Transistor Gate Of A Recessed Access Device, Method Of Forming A Recessed Transistor Gate And A Non-Recessed Transistor Gate, And Method Of Fabricating An Integrated Circuit 有权形成嵌入式接入装置的晶体管栅极的方法，形成嵌入式晶体管栅极和非嵌入晶体管栅极的方法以及制造集成电路的方法公开(公告)号：US20090239366A1
公开(公告)日：2009-09-24
申请号：US12476364
申请日：2009-06-02
申请人： Hasan Nejad , Thomas A. Figura , Gordon A. Haller , Ravi Iyer , John Mark Meldrim , Justin Harnish
发明人： Hasan Nejad , Thomas A. Figura , Gordon A. Haller , Ravi Iyer , John Mark Meldrim , Justin Harnish
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823418 , H01L21/823443 , H01L21/823814 , H01L27/10852 , H01L27/10876 , H01L27/10897 , H01L29/4975 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.
摘要翻译： 为嵌入硅完全硅化提供了方法和结构。 在沟槽内提供硅。 在硅上提供了一种金属混合物，其中一种金属在硅中比硅中更容易扩散到金属中，而另一种金属在硅中比在金属中的硅更容易扩散。 示例性的混合物包括80％的镍和20％的钴。 尽管沟槽的纵横比相对较高，但沟槽内的硅可以完全无硅化物形成。 在其他设备中，可以通过用于存储器阵列的方法形成凹陷接入设备（RAD）。
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公开(公告)号：US07557032B2
公开(公告)日：2009-07-07
申请号：US11219303
申请日：2005-09-01
申请人： Hasan Nejad , Thomas A. Figura , Gordon A. Haller , Ravi Iyer , John Mark Meldrim , Justin Harnish
发明人： Hasan Nejad , Thomas A. Figura , Gordon A. Haller , Ravi Iyer , John Mark Meldrim , Justin Harnish
IPC分类号： H01L21/4763
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823418 , H01L21/823443 , H01L21/823814 , H01L27/10852 , H01L27/10876 , H01L27/10897 , H01L29/4975 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.
摘要翻译： 为嵌入硅完全硅化提供了方法和结构。 在沟槽内提供硅。 在硅上提供了一种金属混合物，其中一种金属在硅中比硅中更容易扩散到金属中，而另一种金属在硅中比在金属中的硅更容易扩散。 示例性的混合物包括80％的镍和20％的钴。 尽管沟槽的纵横比相对较高，但沟槽内的硅可以完全无硅化物形成。 在其他设备中，可以通过用于存储器阵列的方法形成凹陷接入设备（RAD）。
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8.发明授权Method of forming a transistor gate of a recessed access device, method of forming a recessed transistor gate and a non-recessed transistor gate, and method of fabricating an integrated circuit 有权形成凹陷式存取器件的晶体管栅极的方法，形成凹陷晶体管栅极和非凹槽晶体管栅极的方法以及制造集成电路的方法公开(公告)号：US07977236B2
公开(公告)日：2011-07-12
申请号：US12476364
申请日：2009-06-02
申请人： Hasan Nejad , Thomas A. Figura , Gordon A. Haller , Ravi Iyer , John Mark Meldrim , Justin Harnish
发明人： Hasan Nejad , Thomas A. Figura , Gordon A. Haller , Ravi Iyer , John Mark Meldrim , Justin Harnish
IPC分类号： H01L21/4763
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823418 , H01L21/823443 , H01L21/823814 , H01L27/10852 , H01L27/10876 , H01L27/10897 , H01L29/4975 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.
摘要翻译： 为嵌入硅完全硅化提供了方法和结构。 在沟槽内提供硅。 在硅上提供了一种金属混合物，其中一种金属在硅中比硅中更容易扩散到金属中，而另一种金属在硅中比在金属中的硅更容易扩散。 示例性的混合物包括80％的镍和20％的钴。 尽管沟槽的纵横比相对较高，但沟槽内的硅可以完全无硅化物形成。 在其他设备中，可以通过用于存储器阵列的方法形成凹陷接入设备（RAD）。
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公开(公告)号：US07214621B2
公开(公告)日：2007-05-08
申请号：US11131994
申请日：2005-05-18
申请人： Hasan Nejad , Gordon A. Haller , Thomas Arthur Figura , Ravi Iyer
发明人： Hasan Nejad , Gordon A. Haller , Thomas Arthur Figura , Ravi Iyer
IPC分类号： H01L21/8244
CPC分类号： H01L27/10894 , H01L27/10876 , H01L27/10897 , Y10S439/917
摘要： The invention includes methods of forming devices associated with semiconductor constructions. In exemplary methods, common processing steps are utilized to form fully silicided recessed array access gates and partially silicided periphery transistor gates.
摘要翻译： 本发明包括形成与半导体结构相关的器件的方法。 在示例性方法中，利用通常的处理步骤来形成完全硅化的凹陷阵列存取栅极和部分硅化的外围晶体管栅极。
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公开(公告)号：US20070166920A1
公开(公告)日：2007-07-19
申请号：US11716433
申请日：2007-03-08
申请人： Sanh Tang , Gordon Haller , Prashant Raghu , Ravi Iyer
发明人： Sanh Tang , Gordon Haller , Prashant Raghu , Ravi Iyer
IPC分类号： H01L21/336
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66787
摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.
摘要翻译： 晶体管栅极形成方法包括在线路开口内形成金属层，并在金属层的开口内形成填充层。 填充层相对于金属层基本上可选择性地蚀刻。 晶体管结构包括线路开口，开口内的电介质层，开口内的电介质层上的金属层，以及开口内的金属层上的填充层。 如果填充层被金属层的增加的厚度代替，则金属层/填充层组合的内在特性小于否则会存在。 本发明至少应用于三维晶体管结构。
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